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[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors最新文献

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A predictive parallel motion estimation algorithm for digital image processing 一种用于数字图像处理的预测并行运动估计算法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139986
Liang-Gee Chen, Wai-Ting Chen, Yeu-Shen Jehng, T. Chiueh
{"title":"A predictive parallel motion estimation algorithm for digital image processing","authors":"Liang-Gee Chen, Wai-Ting Chen, Yeu-Shen Jehng, T. Chiueh","doi":"10.1109/ICCD.1991.139986","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139986","url":null,"abstract":"An efficient block matching algorithm (BMA) for motion estimation is presented. This BMA exploits motion correlation of neighbor blocks in the temporal direction to reduce the search area. Instead of finding the 2D motion vector directly, this BMA finds two 1D displacements in parallel on two axes independently within the reduced search area. Simulation results show that this algorithm can rival conventional BMAs for performance. The hardware-oriented features of this BMA guarantee that it is more suitable for the hardware realization of a VLSI motion estimator.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129138893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Partitioning sequential circuits for logic optimization 为逻辑优化划分顺序电路
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139848
S. Dey, F. Brglez, G. Kedem
{"title":"Partitioning sequential circuits for logic optimization","authors":"S. Dey, F. Brglez, G. Kedem","doi":"10.1109/ICCD.1991.139848","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139848","url":null,"abstract":"The concepts of corolla partitioning based on an analysis of signal reconvergence to cyclic sequential circuits are extended. The sequential circuit is partitioned into corollas that will contain latches but can be peripherally retimed and resynthesized using combinational techniques. Cycles are broken in the circuit by ensuring that the partitions that are formed are acyclic. Application of the proposed partitioning, retiming and resynthesis approach to a set of large sequential benchmarks has shown considerable gains after resynthesis.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126342128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Design considerations for digital circuit interconnections in a multilayer printed circuit board 多层印刷电路板中数字电路互连的设计考虑
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139949
A. Agrawal, C. S. Chang, D. A. Gernhart
{"title":"Design considerations for digital circuit interconnections in a multilayer printed circuit board","authors":"A. Agrawal, C. S. Chang, D. A. Gernhart","doi":"10.1109/ICCD.1991.139949","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139949","url":null,"abstract":"The design considerations of signal lines in a multilayer printed circuit board are discussed. The effect of the orthogonal lines on the impedance, delay, and signal cross-talk is investigated for a single line and two coupled lines. The effect of loading and cross-over lines in the memory card design is also discussed.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124296102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Area optimization for higher order hierarchical floorplans 高阶分层平面图的面积优化
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139963
Khe-Sing The, D. F. Wong
{"title":"Area optimization for higher order hierarchical floorplans","authors":"Khe-Sing The, D. F. Wong","doi":"10.1109/ICCD.1991.139963","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139963","url":null,"abstract":"The floorplan area optimization problem is to determine the dimensions of each module when the topology of the floorplan is given. The objective is to minimize the area of the resulting floorplan. An algorithm for general hierarchical floorplans is presented. The shape curves for non-slicing configurations are constructed by operations on the graph representations of the floorplan. The points of a shape curve are determined by simultaneously reducing the length of all longest paths of the vertical adjacency graph, using a minimum cut technique. The algorithm is applicable to hierarchical floorplans of high order and to modules with an infinite set of possible dimensions.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124555633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Concurrent resynthesis for network optimization 网络优化的并发再合成
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139841
Kuang-Chien Chen, M. Fujita
{"title":"Concurrent resynthesis for network optimization","authors":"Kuang-Chien Chen, M. Fujita","doi":"10.1109/ICCD.1991.139841","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139841","url":null,"abstract":"An algorithm called C-RENO (Concurrent Resynthesis for Network Optimization) is presented for the optimization of multilevel combinational networks. In C-RENO, a given network is optimized for global optimality by resynthesizing a set of gates concurrently, using other gates in the network. C-RENO uses the generalized ratio-set algorithm, which enables one to resynthesize complex gates instead of only simple gates (e.g. NAND and NOR), exploring larger reconfiguration space. High-quality networks are derived by C-RENO even if no network don't-cares are used, and results which are not achievable by other methods have been obtained.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122779784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A simulator for general purpose optical arrays 通用光学阵列模拟器
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139954
Walter B. Marvin, W. Burleson
{"title":"A simulator for general purpose optical arrays","authors":"Walter B. Marvin, W. Burleson","doi":"10.1109/ICCD.1991.139954","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139954","url":null,"abstract":"Architectures based on optical arrays offer the promise of massive parallelism and three-dimensional computing. The design of an integrated general purpose optical or electrooptical machine is a formidable task. The simulation of these technologies using electronic computers allows a number of designs for such machines to be explored. The general purpose simulator for electrooptical arrays presented demonstrates the practicality and presents the limitations of such technologies. The behavior of bi-level optically active gate and lens materials is simulated as solutions to well-known equations in a low level optical simulation. A second higher level optical simulation is used to simulate optical arrays at the gate level using modified ray tracing techniques. A third level provides a simulation of the electrooptical integration of an example array processor, and allows simulation of machine code for a minimal classical machine to be mapped onto an example array architecture.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"09 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115220336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
VLSI design automation for the application system/400 VLSI设计自动化应用系统/400
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139943
R. F. Lembach, J. Borkenhagen, John R. Elliott, Randall A. Schmidt
{"title":"VLSI design automation for the application system/400","authors":"R. F. Lembach, J. Borkenhagen, John R. Elliott, Randall A. Schmidt","doi":"10.1109/ICCD.1991.139943","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139943","url":null,"abstract":"The VLSI design automation process for the IBM AS/400 is highly focused on the dual goals of short design time and exhaustive verification. Some of the recent developments in the process areas of high level language and synthesis, timing analysis and verification, chip physical design, and system testing are described. The process continues to evolve to meet the dual challenges of shorter design time and improved solution quality.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127055212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A provable near-optimal algorithm for the channel pin assignment problem 通道引脚分配问题的一种可证明的近最优算法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139907
J. Cong, Kei-Yong Khoo
{"title":"A provable near-optimal algorithm for the channel pin assignment problem","authors":"J. Cong, Kei-Yong Khoo","doi":"10.1109/ICCD.1991.139907","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139907","url":null,"abstract":"A near-optimal algorithm for the channel pin assignment problem is presented. This algorithm, called the alternative packing algorithm, can always produce an assignment solution whose density is at most one more than the density of an optimal solution, i.e., d(S)<or=d(S*)+1, where d(S) is the density of this solution and d(S*) is the density of the optimal solution. The algorithm is tested on a number of channel routing benchmark examples and achieved significant reduction in channel density and total net span. The algorithm has important applications to the pin assignment and global routing problems in general cell layout design since it is shown that the combined pin assignment and global routing problem can be reduced to a series of channel pin assignment problems.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127514929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A formally verified system for logic synthesis 一个经过正式验证的逻辑综合系统
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139915
M. Aagaard, M. Leeser
{"title":"A formally verified system for logic synthesis","authors":"M. Aagaard, M. Leeser","doi":"10.1109/ICCD.1991.139915","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139915","url":null,"abstract":"The correctness of a logic synthesis system is implemented and proved. The algorithm is based on the weak division algorithm for Boolean simplification previously presented. The implementation is in the programming language ML; and the proof is in the Nuprl proof development system. This study begins with a proof of the algorithm previously presented and extends it to a level of detail sufficient for proving the implementation of the system. In the process of developing the proof many definitions presented in previous accounts of the algorithms were clarified, and several errors in the implementation were discovered. The result is that the designs generated by the implementation can be claimed to be correct by construction, since the correctness of the system was proven.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121455979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Aliasing probability in multiple input linear signature automata for q-ary symmetric errors 多输入线性签名自动机中q元对称误差的混叠概率
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139917
G. Edirisooriya, John P. Robinson
{"title":"Aliasing probability in multiple input linear signature automata for q-ary symmetric errors","authors":"G. Edirisooriya, John P. Robinson","doi":"10.1109/ICCD.1991.139917","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139917","url":null,"abstract":"The aliasing probability in single and multiple input linear automata signature registers (LASRs: linear feedback shift registers (LFSRs) and linear cellular automata) has been widely studied under the independent bit error model. Aliasing in a class of multiple-input LASRs (MILASRs) under the q-ary symmetric error model is examined. By modeling the signature analyzer as a two state Markov process, it is shown that the closed form expression previously derived for aliasing probability for multiple-input LFSRs with primitive polynomials holds for a far more general class of linear automata signature analyzers, including all multiple-input LFSRs. An easily verifiable criterion is given to determine whether a MILASR falls into this category. It is shown that for q-ary symmetric errors, the circuit complexity and the propagation delay can be minimized by using a set of m single bit LFSRs.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"313 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115023843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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