{"title":"关键网络路由","authors":"J. Cohoon, L. J. Randall","doi":"10.1109/ICCD.1991.139875","DOIUrl":null,"url":null,"abstract":"A critical net has been routed traditionally by interconnecting its terminals with a minimum length rectilinear Steiner tree (MRST). A novel interconnection form, the maximum performance tree (MPT), that better approximates an interconnection with optimal circuit performance is proposed. In addition, a heuristic approach is presented that quickly generates MPTs, and the quality of these trees is compared with MRSTs for several net instances.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"37","resultStr":"{\"title\":\"Critical net routing\",\"authors\":\"J. Cohoon, L. J. Randall\",\"doi\":\"10.1109/ICCD.1991.139875\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A critical net has been routed traditionally by interconnecting its terminals with a minimum length rectilinear Steiner tree (MRST). A novel interconnection form, the maximum performance tree (MPT), that better approximates an interconnection with optimal circuit performance is proposed. In addition, a heuristic approach is presented that quickly generates MPTs, and the quality of these trees is compared with MRSTs for several net instances.<<ETX>>\",\"PeriodicalId\":239827,\"journal\":{\"name\":\"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-10-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"37\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.1991.139875\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.1991.139875","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A critical net has been routed traditionally by interconnecting its terminals with a minimum length rectilinear Steiner tree (MRST). A novel interconnection form, the maximum performance tree (MPT), that better approximates an interconnection with optimal circuit performance is proposed. In addition, a heuristic approach is presented that quickly generates MPTs, and the quality of these trees is compared with MRSTs for several net instances.<>