System level ASIC design for Hewlett-Packard's low cost PA-RISC workstations

Abstract

The system architecture of a low cost PA-RISC workstation is described. This architecture is implemented in Hewlett-Packard's 9000 series 700 workstations. High performance and low cost are achieved through careful system partitioning and appropriate application of integration. The system design involved the development of four ASICs: a memory I/O system controller, a mixing buffer chip, a DRAM address decoder/buffer chip, and a controller for the built-in I/O functions. The system architecture is optimized to maximize performance for workstation workloads which include an emphasis on raw CPU performance, graphics, and I/O throughput.<>