Gigascale integration (GIS) in the 21st century

Summary form only given. Opportunities for incorporation of more than one billion transistors and associated interconnections with a single silicon chip or for gigascale integration (GSI) are governed by a hierarchy of limits whose levels can be codified as fundamental, material, device, circuit, and system. Each level of this hierarchy includes both theoretical and practical limits. Theoretical limits are determined solely by physical principles. Practical limits are strongly influenced by manufacturing technology and markets and can be described in terms of the minimum feature size, the square root of die area, and the packing efficiency (defined as the number of transistors or components per minimum feature area). The singular metric that reveals the efficacy of a technology for GSI is the chip performance index (CPI) defined as the quotient of the number of transistors per chip (N) and the associated power-delay product (Pt/sub d/) or CPI=N/Pt/sub d/. The CPI increased by about 10/sup 13/ from 1960 to 1990 and is projected to increase by another factor of 10/sup 6/ from 1990 to 2020.<>