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[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors最新文献

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Design and synthesis of self-checking VLSI circuits and systems VLSI自检电路与系统的设计与合成
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139977
N. Jha, Sying-Jyan Wang
{"title":"Design and synthesis of self-checking VLSI circuits and systems","authors":"N. Jha, Sying-Jyan Wang","doi":"10.1109/ICCD.1991.139977","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139977","url":null,"abstract":"Self-checking circuits and systems can detect the presence of both transient and permanent faults. The advantage of such a system is that errors can be caught as soon as they occur, and thus data contamination is prevented. Although much effort has been concentrated on the design of self-checking checkers by previous researchers, very few results have been presented for the design of self-checking functional circuits, and fewer still for the design of self-checking systems. Methods are explored for the cost-effective design of combinational and sequential functional circuits, checkers and systems.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127411021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Fault-tolerant model of neural computing 神经计算的容错模型
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139860
Lon-Chan Chu
{"title":"Fault-tolerant model of neural computing","authors":"Lon-Chan Chu","doi":"10.1109/ICCD.1991.139860","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139860","url":null,"abstract":"A fault-tolerant model of feed-forward neural computing with mixed-mode redundancy is proposed and analyzed. A mixed-mode redundancy is a combination of spatial redundancy and temporal redundancy. The redundancy is based on the homogeneity of both structures and operations of neurons in neural networks. This fault-tolerant model can be applied to both hardware architecture and parallel software simulation. By storing multiple sets of weights in a neuron and recomputing the outputs of this neuron at other different neurons, faults in the neuron can be detected and the output errors can be corrected. The degree of the fault tolerance of this model is analyzed. Further, the sufficient conditions for detecting errors and recovering outputs are also presented. The model can highly increase the reliability of neural computing so that a fairly large number of faulty neurons can be detected and that the outputs of these faulty neurons can be recovered.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115676356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Incremental synthesis for engineering changes 工程变更的增量综合
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139840
Yosinori Watanabe, R. Brayton
{"title":"Incremental synthesis for engineering changes","authors":"Yosinori Watanabe, R. Brayton","doi":"10.1109/ICCD.1991.139840","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139840","url":null,"abstract":"The problem of rectifying design incorrectness due to specification changes as well as design errors of VLSI circuits is formulated and a basic approach using logic synthesis techniques is presented. An efficient approach is presented for rectifying the functional incorrectness by attaching circuitry exterior to the original design. A necessary and sufficient condition for full rectification of the design is provided. It is shown that the proposed approach always succeeds in the rectification of arbitrary combinational circuits. The situation where rectification arises in a practical design process is briefly reviewed.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114864979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
Modeling of interconnection lines for simulation of VLSI circuits VLSI电路仿真中互连线路的建模
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139852
Felipe S. Santos, J. Swart
{"title":"Modeling of interconnection lines for simulation of VLSI circuits","authors":"Felipe S. Santos, J. Swart","doi":"10.1109/ICCD.1991.139852","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139852","url":null,"abstract":"A modeling approach for RC delays of interconnection lines, based on a lumped resistor and capacitor ladder, for the distributed RC transmission line, is presented. The interconnection line is considered to be driven by a MOS gate source, MOS gate loads, and RC interconnection branches. The minimum number of required RC sections is obtained for each case of driving an interconnection line and for a specified average relative error. Also, a rule based on the worst case of driving an interconnection branch in a complex RC tree network is proposed in order to automatically determine the recommended number of RC sections. This can be used as a first step before timing simulations.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115122915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Verification techniques for a MIPS compatible embedded control processor MIPS兼容嵌入式控制处理器的验证技术
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139910
Darren Jones, R. Yang, M. Kwong, George Harper
{"title":"Verification techniques for a MIPS compatible embedded control processor","authors":"Darren Jones, R. Yang, M. Kwong, George Harper","doi":"10.1109/ICCD.1991.139910","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139910","url":null,"abstract":"The methods used in the verification of a MIPS-1 architecture-compatible embedded control processor are described. This single-chip processor contains 700000 transistors, operates at 50 MHz, and consists of a CPU core, 8 kB of instruction cache, 1 kB of data cache, a DRAM controller, a write buffer, three timers, and a bus interface unit (BIU). Individual module testing and integrated system testing were the two methods used for verification. Integrated system simulation included architectural, functional, and random instruction testing using behavioral simulation test environments. These techniques provided a comprehensive and effective testing environment. The transfer of fully functional rev A silicon to production demonstrated the success of this methodology.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123687860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A technique for generating efficient simulators 一种生成高效模拟器的技术
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139855
P. Bakowski, J. Dubois, A. Pawlak
{"title":"A technique for generating efficient simulators","authors":"P. Bakowski, J. Dubois, A. Pawlak","doi":"10.1109/ICCD.1991.139855","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139855","url":null,"abstract":"A methodology is presented aimed at reducing the size of generated simulators and at increasing their simulation speed. This technique consists in abstracting the functionality of an architecture's control part into a data table and mapping it onto the main memory of a host computer. The Lille University simulator called LIDO was used as a testbed for experiments. Some decision making capabilities of the generator based on static analysis of characteristics of an architecture and empirically refined are presented. Results of comparative tests with a VHDL simulator are discussed.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121923526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Robust path delay-fault testability on dynamic CMOS circuits 动态CMOS电路的鲁棒路径延迟故障可测试性
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139882
P. McGeer
{"title":"Robust path delay-fault testability on dynamic CMOS circuits","authors":"P. McGeer","doi":"10.1109/ICCD.1991.139882","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139882","url":null,"abstract":"The properties of delay-fault testability on dynamic CMOS logic circuits are investigated. It is demonstrated that the concepts of static sensitizability and robust path delay-fault (RPDF) testability are synonymous on these circuits, and that hence RPDF testability is somewhat easier on these circuits than on static logic circuits. It is also argued that a less restrictive testability condition than the RPDF criterion detects all path delay-faults which will affect the operation of the circuit. It is shown that the set of test vectors which satisfies this less-restrictive condition is exactly the union of the on-sets of the primary circuit outputs.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124038731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Illustration of the SFG-tracing multi-level behavioral verification methodology, by the correctness proof of a high to low level synthesis application in Cathedral-II 说明sfg跟踪多层次的行为验证方法，通过在Cathedral-II中一个从高到低层次的合成应用的正确性证明
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139913
M. Genoe, L. Claesen, E. Verlind, F. Proesmans, H. Man
{"title":"Illustration of the SFG-tracing multi-level behavioral verification methodology, by the correctness proof of a high to low level synthesis application in Cathedral-II","authors":"M. Genoe, L. Claesen, E. Verlind, F. Proesmans, H. Man","doi":"10.1109/ICCD.1991.139913","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139913","url":null,"abstract":"The SFG-tracing methodology addresses the automatic verification of digital synchronous circuit implementations as specified at the algorithmic level as signal- (SFG) or data flow graphs. The SFG-tracing methodology is a multi-level design verification paradigm that aims at bridging the gap between higher level specifications down to lower level implementations up to the transistor switch level. The concepts of the SFG-tracing methodology are illustrated by the automatic verification of a transistor level implementation of a small chip generated from its high level specification by the Cathedral-II silicon compiler. This application, although simple, includes a datapath, register files, a multi-branch micro coded controller, and additional circuitry as necessary for design for testability measures. This application illustrates the SFG-tracing verification methodology as applied to one member of a partitioned SFG behavioral specification. Experimental results on more complex, completely verified designs of 32000 transistors demonstrate the feasibility of the approach.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128745825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Synthesis of asynchronous state machines using a local clock 使用本地时钟的异步状态机的合成
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139879
S. Nowick, D. Dill
{"title":"Synthesis of asynchronous state machines using a local clock","authors":"S. Nowick, D. Dill","doi":"10.1109/ICCD.1991.139879","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139879","url":null,"abstract":"A novel, correct design methodology for asynchronous state-machine controllers is presented. The goal of this work is a design style as close to a synchronous one as possible, but with the advantages of an asynchronous method. The implementations realize asynchronous state-machine specifications using standard combinational logic, flow latches as storage elements, and a locally-generated clocking signal that pulses whenever there is a change in state. This design style allows multiple input changes which can arrive at arbitrary times. The implementations use a minimal or near-minimal number of states. It also allows arbitrary state encoding and flexibility in logic minimization and gate-level realization, so it can take advantage of systematic CAD optimization techniques.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130880782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 112
Liquid nitrogen CMOS for computer applications 计算机应用的液氮CMOS
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139827
F. Gaensslen, D. D. Meyer
{"title":"Liquid nitrogen CMOS for computer applications","authors":"F. Gaensslen, D. D. Meyer","doi":"10.1109/ICCD.1991.139827","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139827","url":null,"abstract":"Past and present development in the field of operating microelectronic computer circuits at liquid nitrogen temperature (LNT) are reviewed. To assess the potential of this technology, its advantages and disadvantages are discussed. The fact that devices and materials behave generically better at low temperature will have some bearing on the ultimate attainable technology limits. The optimized complementary metal oxide semiconductor (CMOS) system advantages at LNT are analyzed. The basic conclusion is that the liquid nitrogen CMOS (LNCMOS) is a viable system technology for commercial and military computer systems.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"293 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115826374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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