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[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors最新文献

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Test and validation for Monsoon processing elements 季风处理要素的测试和验证
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139871
M. Beckerle, G. Papadopoulos
{"title":"Test and validation for Monsoon processing elements","authors":"M. Beckerle, G. Papadopoulos","doi":"10.1109/ICCD.1991.139871","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139871","url":null,"abstract":"An aggressive, integrated hardware/software approach for the test and validation of Monsoon processing elements is developed. The strategy comprises three main elements: scan-paths of internal processor state, gate-level simulator of the entire processing element for hardware timing verification, and a novel table-driven instruction-level interpreter. Each of these elements is detailed, and it is shown how they contribute to design, test, validation, and debug.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"268 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115964288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SYNTEST: a method for high-level SYNthesis with self-TESTability SYNTEST:一种具有自测试性的高级合成方法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139947
Christos A. Papachristou, S. Chiu, Haidar Harmanani
{"title":"SYNTEST: a method for high-level SYNthesis with self-TESTability","authors":"Christos A. Papachristou, S. Chiu, Haidar Harmanani","doi":"10.1109/ICCD.1991.139947","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139947","url":null,"abstract":"The article introduces a new high-level synthesis method for self-testable RTL designs. A basic feature of this method is a structural testability model which treats testability as a structural design style integrated in the design process. The main objective is to develop a system-level synthesis tool set mapping a behavioral description onto an optimized and testable RTL design subject to user-defined constraints. The approach involves several major components within the following system-level iteration: scheduling and allocation, constraint estimation, and testability tradeoffs.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"254 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121811831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The commercial realization of multi-chip modules quo vadimus 多芯片模块的商业实现还处于起步阶段
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139982
R. Hendel
{"title":"The commercial realization of multi-chip modules quo vadimus","authors":"R. Hendel","doi":"10.1109/ICCD.1991.139982","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139982","url":null,"abstract":"Multi-chip modules (MCMs) have the potential to lead the semiconductor industry to the next level of functional integration. The design, implementation and successful realization of commercially viable modules are still elusive. Factors affecting the commercial viability of this technology are discussed. These factors include design and modeling, substrate fabrication, testing of substrates and modules, and assembly of MCM modules.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"275 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122751463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
VLSI implementation of a new block cipher VLSI实现的一种新的分组密码
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139960
H. Bonnenberg, A. Curiger, N. Felber, H. Kaeslin, Xuejia Lai
{"title":"VLSI implementation of a new block cipher","authors":"H. Bonnenberg, A. Curiger, N. Felber, H. Kaeslin, Xuejia Lai","doi":"10.1109/ICCD.1991.139960","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139960","url":null,"abstract":"The high speed architecture for a VLSI implementation of a new smart-key block cipher is presented. The chip performs data encryption and decryption in a single hardware unit. It runs with a maximum clock frequency of 33 MHz permitting a data conversion rate of more than 55 Mb/s. This high data rate, compared to currently available DES (data encryption standard) implementations, has been achieved by implementing a pipelined architecture and by using a sophisticated data scheduling scheme guaranteeing a continuously fully loaded pipeline.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132202565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Neural networks update 神经网络更新
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139829
E. S. Kirkpatrick
{"title":"Neural networks update","authors":"E. S. Kirkpatrick","doi":"10.1109/ICCD.1991.139829","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139829","url":null,"abstract":"Summary form only given, as follows. Neural networks have been intensively studied as a discipline in their own right in the last five years (late 1980s, early 1990s). Initial claims were extremely ambitious; by using the brain's computing principles, networks would eliminate programming, revolutionize computer architecture and sensor interfacing, make analog VLSI a reality, and give guidance to a new understanding of human cognition. Work in two areas is described: statistical methods to deal with classification, prediction, and control in data-rich, intuition-poor problems; and VLSI solutions, both in digital and analog styles, to accommodate these architectures.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134124133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power play-fast dynamic power estimation based on logic simulation 基于逻辑仿真的快速动态功率估计
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139853
Thomas H. Krodel
{"title":"Power play-fast dynamic power estimation based on logic simulation","authors":"Thomas H. Krodel","doi":"10.1109/ICCD.1991.139853","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139853","url":null,"abstract":"A fast algorithm and a tool for the estimation of dynamic power dissipation in digital circuits are presented. The logic waveforms generated by a standard logic simulator are used in order to compute an instantaneous power waveform at the gate- (cell-) level. The tool itself is technology independent; it takes parameters for the currently used cell library from a database that has been established by analog simulation. Modeling of new libraries is easy due to a flexible database format. When compared to SPICE, experimental results show good accuracy for average power consumption ( Delta <3%), a close matching of peak power values and a speed-up of more than four orders of magnitude.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114491768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Fault tolerant VLSI design with functional block redundancy 功能块冗余容错VLSI设计
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139938
R. Ernst, P. Nowottnick
{"title":"Fault tolerant VLSI design with functional block redundancy","authors":"R. Ernst, P. Nowottnick","doi":"10.1109/ICCD.1991.139938","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139938","url":null,"abstract":"Functional block redundancy is a dynamic redundancy technique for fault tolerance of VLSI circuits with nonregular logic structure, such as gate array designs. It exploits functional similarity of subcircuits, such as repeatedly used counter and shift register functions, to reduce the overhead of standby modules. The example of a manually optimized industrial gate array shows an extremely low overhead factor of 1.8 for complete single fault tolerance, which previously could not be reached for this type of circuit.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121913122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The cycle structure of channel graphs in nonsliceable floorplans and a unified algorithm for feasible routing order 不可切片平面中通道图的循环结构及可行路由顺序的统一算法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139964
S. Sur-Kolay, B. Bhattacharya
{"title":"The cycle structure of channel graphs in nonsliceable floorplans and a unified algorithm for feasible routing order","authors":"S. Sur-Kolay, B. Bhattacharya","doi":"10.1109/ICCD.1991.139964","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139964","url":null,"abstract":"Channel graphs for nonsliceable floorplans are studied for determination of feasible channel routing order. The minimum feedback vertex set (MFVS) formulation is revisited and a polynomial time heuristic is presented. It is shown that feasible routing orders with reserved channels, L-channels, and monotone channels can be obtained from a given MFVS for any floorplan. This approach provides a powerful tool to unify all three previous approaches and produces a solution with comparable efficiency and quality.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122131824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Logic design for a high performance mainframe computer-the HITAC M-880 processor 高性能大型机——HITAC M-880处理器的逻辑设计
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139833
Y. Shintani, Kiyoshi Inoue, T. Shonai, K. Wada, S. Abe, Katsuro Wakai
{"title":"Logic design for a high performance mainframe computer-the HITAC M-880 processor","authors":"Y. Shintani, Kiyoshi Inoue, T. Shonai, K. Wada, S. Abe, Katsuro Wakai","doi":"10.1109/ICCD.1991.139833","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139833","url":null,"abstract":"Logic design and its effects on the HITAC M-880 basic scalar processor are described. The M-880 is a high end mainframe computer which uses current high speed circuits and packaging technologies, as well as logic methods, to improve performance. An optimal pipeline stage evaluation method is proposed, together with a new cache access method termed merge access. The combined effect of the logic methods is a 10% improvement in processor performance with online transaction processing.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122927079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Overview of the Monsoon project 季风项目概述
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139869
K. R. Traub, G. Papadopoulos, M. Beckerle, James E. Hicks, Jonathan Young
{"title":"Overview of the Monsoon project","authors":"K. R. Traub, G. Papadopoulos, M. Beckerle, James E. Hicks, Jonathan Young","doi":"10.1109/ICCD.1991.139869","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139869","url":null,"abstract":"Monsoon is an experimental multi-threaded multiprocessor targeted to large-scale, general purpose scientific and symbolic computations. In particular, Monsoon is designed for the efficient execution of code compiled from Id, a high-level, implicitly parallel declarative language. Monsoon is a product of a multiyear cooperative research and development program between the Massachusetts Institute of Technology (MIT) and Motorola, Inc., which, in turn is an outgrowth of over ten years of research in dynamic dataflow architectures and languages conducted at MIT. The intent is to provide an overall view of the Monsoon hardware and software system architecture. In addition, the run-time system and emulator are detailed.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124174510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
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