{"title":"季风处理要素的测试和验证","authors":"M. Beckerle, G. Papadopoulos","doi":"10.1109/ICCD.1991.139871","DOIUrl":null,"url":null,"abstract":"An aggressive, integrated hardware/software approach for the test and validation of Monsoon processing elements is developed. The strategy comprises three main elements: scan-paths of internal processor state, gate-level simulator of the entire processing element for hardware timing verification, and a novel table-driven instruction-level interpreter. Each of these elements is detailed, and it is shown how they contribute to design, test, validation, and debug.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"268 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Test and validation for Monsoon processing elements\",\"authors\":\"M. Beckerle, G. Papadopoulos\",\"doi\":\"10.1109/ICCD.1991.139871\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An aggressive, integrated hardware/software approach for the test and validation of Monsoon processing elements is developed. The strategy comprises three main elements: scan-paths of internal processor state, gate-level simulator of the entire processing element for hardware timing verification, and a novel table-driven instruction-level interpreter. Each of these elements is detailed, and it is shown how they contribute to design, test, validation, and debug.<<ETX>>\",\"PeriodicalId\":239827,\"journal\":{\"name\":\"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors\",\"volume\":\"268 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-10-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.1991.139871\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.1991.139871","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Test and validation for Monsoon processing elements
An aggressive, integrated hardware/software approach for the test and validation of Monsoon processing elements is developed. The strategy comprises three main elements: scan-paths of internal processor state, gate-level simulator of the entire processing element for hardware timing verification, and a novel table-driven instruction-level interpreter. Each of these elements is detailed, and it is shown how they contribute to design, test, validation, and debug.<>