发布求助
文献互助 智能选刊 最新文献

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors最新文献

筛选
英文 中文
Energy considerations in multichip-module based multiprocessors 基于多芯片模块的多处理器中的能量考虑
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139981
J. Burr, A. Peterson
{"title":"Energy considerations in multichip-module based multiprocessors","authors":"J. Burr, A. Peterson","doi":"10.1109/ICCD.1991.139981","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139981","url":null,"abstract":"Multichip modules permit highly efficient implementation of tiled architectures. If the tiles are implemented in submicron CMOS, extremely highly computation rates can be achieved, but power dissipation becomes the principal factor limiting achievable levels of integration and performance. Some examples of tiled architectures are described. The feasibility and advantages of reduced voltage operation for reducing energy per operation in power constrained environments are discussed.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126324281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Concurrent error detection in array dividers by alternating input data 交替输入数据的阵列除法器并发错误检测
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139858
C. Wey
{"title":"Concurrent error detection in array dividers by alternating input data","authors":"C. Wey","doi":"10.1109/ICCD.1991.139858","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139858","url":null,"abstract":"Concurrent error detection (CED) schemes utilizing time redundancy can keep chip area and interconnect to a minimum. An efficient time redundancy scheme, RESO, for array dividers has been reported. Under the same cell fault model, an alternated time redundancy CED scheme using an alternating logic (AL) approach is proposed. The key to the detection of faults using the AL approach is determining that at least one input combination exists for which the error does not result in alternating outputs. Results of this study show that the proposed design achieves the same CED capability as RESO implementation yet with a lower area overhead. Due to the simplicity and low area overhead the proposed AL approach will be very attractive for the design of fault-tolerant VLSI-based systems.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129827129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Object caching for performance in object-oriented systems 对象缓存在面向对象系统中的性能
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139924
J. M. Chang, E. Gehringer
{"title":"Object caching for performance in object-oriented systems","authors":"J. M. Chang, E. Gehringer","doi":"10.1109/ICCD.1991.139924","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139924","url":null,"abstract":"Object-oriented systems exhibit a very high rate of object creation, but most objects are short-lived. As a result, memory-management overhead is significant. An application-specific coprocessor architecture to speed up object creation and memory reclamation in object-oriented systems is described. The architecture supports a bit-vector approach to dynamic storage allocation and liberation. Novel created objects reside in a cache that is reference counted. Most objects are expected to die before they age out of the cache, drastically reducing the number of references to main memory. Many existing computer architectures would require only minor compiler modification to incorporate and benefit from this coprocessor.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"201 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127410676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
F-RISC/G: AlGaAs/GaAs HBT standard cell library F-RISC/G: AlGaAs/GaAs HBT标准细胞库
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139902
K. Nah, R. Philhower, J. V. Etten, S. Simmons, V. Tsinker, James Loy, H. Greub, J. McDonald
{"title":"F-RISC/G: AlGaAs/GaAs HBT standard cell library","authors":"K. Nah, R. Philhower, J. V. Etten, S. Simmons, V. Tsinker, James Loy, H. Greub, J. McDonald","doi":"10.1109/ICCD.1991.139902","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139902","url":null,"abstract":"A standard cell library for implementing Rensselaer's fast reduced instruction set computer (F-RISC/G) project with Rockwell's AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology is presented. The processor is targeted at an instruction cycle time of 1.0 ns. Differential current mode logic (CML) is used, and unloaded gate delays are 15-20 ps.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114907673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An integrated design environment for application specific integrated processor 针对特定应用的集成处理器的集成设计环境
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139933
J. Sato, M. Imai, Tetsuya Hakata, A. Alomary, N. Hikichi
{"title":"An integrated design environment for application specific integrated processor","authors":"J. Sato, M. Imai, Tetsuya Hakata, A. Alomary, N. Hikichi","doi":"10.1109/ICCD.1991.139933","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139933","url":null,"abstract":"A novel framework for ASIP (application specific integrated processor) development is proposed. The system accepts a set of example programs written in the C language and their expected data as input, and profiles these programs both statically and dynamically. Then taking advantage of the profiled results, the system decides the instruction set and hardware architectures of ASIP, and synthesizes the CPU core design of the ASIP, as well as the software development tools for the ASIP such as compiler and simulator.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130459884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
Amdahl chip delay test system Amdahl芯片延迟测试系统
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139881
I. Deol, C. Mallipeddi, T. Ramakrishnan
{"title":"Amdahl chip delay test system","authors":"I. Deol, C. Mallipeddi, T. Ramakrishnan","doi":"10.1109/ICCD.1991.139881","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139881","url":null,"abstract":"The design and implementation of an automatic chip delay test system (CDTS) are described. CDTS has been in use at Amdahl Corporation for over a year and has generated delay tests for about 180 designs ranging from 1000 to 30000 gates, achieving high fault coverage. These designs contain sequential logic and memory elements like random access memories (RAMs). CDTS uses a new scheme for applying delay tests in sequential circuits. The fault model and the delay test generation algorithm used by CDTS are described, and the results of production runs are presented.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131653103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A new O(n log n) scheduling heuristic for parallel decomposition of sparse matrices 一种新的O(n log n)调度启发式稀疏矩阵并行分解算法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139985
R. Telichevesky, P. Agrawal, J. Trotter
{"title":"A new O(n log n) scheduling heuristic for parallel decomposition of sparse matrices","authors":"R. Telichevesky, P. Agrawal, J. Trotter","doi":"10.1109/ICCD.1991.139985","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139985","url":null,"abstract":"The problem of sparse matrix decomposition using distributed memory multiprocessors is addressed. The data partitioning scheme is simple and is based on equalizing the load among the processors. A new O(n log n) task scheduling heuristic with provably deadlock-free properties is presented. The key idea is the ordering of nodes in a task graph that represents the matrix decomposition steps in a levelized manner, based on a new measure, delta the remaining completion time. The method tends to minimize the idle time of processors by revising the overall decomposition schedule by permitting the execution of tasks within these idle periods. For large sparse matrices, the analysis and simulation results show that a multiprocessor with even a small number of processors will exceed the performance of a supercomputer like the Cray X-MP.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131843100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Retiming of circuits with single phase transparent latches
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139850
Narendra V. Shenoy, R. Brayton, A. Sangiovanni-Vincentelli
{"title":"Retiming of circuits with single phase transparent latches","authors":"Narendra V. Shenoy, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/ICCD.1991.139850","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139850","url":null,"abstract":"An algorithm is developed for the retiming of single phase sequential circuits with level sensitive (transparent) latches. A set of constraints that permit retiming and optimal clock cycle computation are also developed. It is shown that a design with edge-triggered latches may be tested for speed-up using transparent latches.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121393773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
An algorithm for the multi-level minimization of Reed-Muller representations Reed-Muller表示的多级最小化算法
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139990
J. Saul
{"title":"An algorithm for the multi-level minimization of Reed-Muller representations","authors":"J. Saul","doi":"10.1109/ICCD.1991.139990","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139990","url":null,"abstract":"There is interest currently in using Reed-Muller equations as a way of representing and manipulating switching functions, and as a means of designing circuits based on exclusive-OR gates. There are only two-level Reed-Muller minimizers in use, although the need for a multi-level minimizer has been identified. A procedure for multi-level Reed-Muller minimization has been developed. It introduces a Reed-Muller factored form and uses algebraic algorithms for factorization decomposition, resubstitution, collapsing, and extraction of common cubes and sub-expressions. The procedure has been implemented in C as a series of packages which have been added to MISII, and benchmark comparisons with minimal two-level representations are favorable.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115969384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A compositional transformation for formal verification 用于形式验证的组合转换
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI: 10.1109/ICCD.1991.139890
E. Cerny
{"title":"A compositional transformation for formal verification","authors":"E. Cerny","doi":"10.1109/ICCD.1991.139890","DOIUrl":"https://doi.org/10.1109/ICCD.1991.139890","url":null,"abstract":"The conditions under which a conjunction of two relations aR/sub 1/b and bR/sub 2/c with existential abstraction of b can be transformed into an implication aR/sub 1/b to bR/sub 2/c with universal abstraction of b are determined. In algorithmic design verification based on tautology checking and automata equivalence this transformation allows one to derive new verification algorithms, and to show under which conditions the breadth-first symbolic reachability algorithm used in proving automata equivalence can be applied when the automata are nondeterministic. Boolean characteristic functions of relations that have efficient representation using binary decision diagrams are used in the derivations.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117175928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信