Amdahl chip delay test system

Abstract

The design and implementation of an automatic chip delay test system (CDTS) are described. CDTS has been in use at Amdahl Corporation for over a year and has generated delay tests for about 180 designs ranging from 1000 to 30000 gates, achieving high fault coverage. These designs contain sequential logic and memory elements like random access memories (RAMs). CDTS uses a new scheme for applying delay tests in sequential circuits. The fault model and the delay test generation algorithm used by CDTS are described, and the results of production runs are presented.<>