Amdahl芯片延迟测试系统

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI:10.1109/ICCD.1991.139881

I. Deol, C. Mallipeddi, T. Ramakrishnan

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引用次数: 4

摘要

介绍了一种自动芯片延迟测试系统(CDTS)的设计与实现。CDTS已经在Amdahl公司使用了一年多，并为大约180种设计生成了延迟测试，范围从1000到30000门，实现了高故障覆盖率。这些设计包含顺序逻辑和存储器元素，如随机存取存储器(ram)。CDTS采用了一种新的延时测试方案，用于时序电路的延时测试。介绍了CDTS所采用的故障模型和延迟测试生成算法，并给出了生产运行的结果。

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Amdahl chip delay test system

The design and implementation of an automatic chip delay test system (CDTS) are described. CDTS has been in use at Amdahl Corporation for over a year and has generated delay tests for about 180 designs ranging from 1000 to 30000 gates, achieving high fault coverage. These designs contain sequential logic and memory elements like random access memories (RAMs). CDTS uses a new scheme for applying delay tests in sequential circuits. The fault model and the delay test generation algorithm used by CDTS are described, and the results of production runs are presented.<>

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来源期刊

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

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