{"title":"基于多芯片模块的多处理器中的能量考虑","authors":"J. Burr, A. Peterson","doi":"10.1109/ICCD.1991.139981","DOIUrl":null,"url":null,"abstract":"Multichip modules permit highly efficient implementation of tiled architectures. If the tiles are implemented in submicron CMOS, extremely highly computation rates can be achieved, but power dissipation becomes the principal factor limiting achievable levels of integration and performance. Some examples of tiled architectures are described. The feasibility and advantages of reduced voltage operation for reducing energy per operation in power constrained environments are discussed.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"95 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":"{\"title\":\"Energy considerations in multichip-module based multiprocessors\",\"authors\":\"J. Burr, A. Peterson\",\"doi\":\"10.1109/ICCD.1991.139981\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Multichip modules permit highly efficient implementation of tiled architectures. If the tiles are implemented in submicron CMOS, extremely highly computation rates can be achieved, but power dissipation becomes the principal factor limiting achievable levels of integration and performance. Some examples of tiled architectures are described. The feasibility and advantages of reduced voltage operation for reducing energy per operation in power constrained environments are discussed.<<ETX>>\",\"PeriodicalId\":239827,\"journal\":{\"name\":\"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors\",\"volume\":\"95 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-10-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"34\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.1991.139981\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.1991.139981","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Energy considerations in multichip-module based multiprocessors
Multichip modules permit highly efficient implementation of tiled architectures. If the tiles are implemented in submicron CMOS, extremely highly computation rates can be achieved, but power dissipation becomes the principal factor limiting achievable levels of integration and performance. Some examples of tiled architectures are described. The feasibility and advantages of reduced voltage operation for reducing energy per operation in power constrained environments are discussed.<>