F-RISC/G: AlGaAs/GaAs HBT standard cell library

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI:10.1109/ICCD.1991.139902

K. Nah, R. Philhower, J. V. Etten, S. Simmons, V. Tsinker, James Loy, H. Greub, J. McDonald

引用次数: 8

Abstract

A standard cell library for implementing Rensselaer's fast reduced instruction set computer (F-RISC/G) project with Rockwell's AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology is presented. The processor is targeted at an instruction cycle time of 1.0 ns. Differential current mode logic (CML) is used, and unloaded gate delays are 15-20 ps.<>

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F-RISC/G: AlGaAs/GaAs HBT标准细胞库

采用罗克韦尔公司的AlGaAs/GaAs异质结双极晶体管(HBT)技术实现伦斯勒公司的快速精简指令集计算机(F-RISC/G)项目的标准单元库。处理器的目标指令周期时间为1.0 ns。采用差分电流模式逻辑(CML)，卸载门延迟为15- 20ps

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

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