SYNTEST:一种具有自测试性的高级合成方法

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI:10.1109/ICCD.1991.139947

Christos A. Papachristou, S. Chiu, Haidar Harmanani

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引用次数: 4

摘要

本文介绍了一种新的自检测RTL设计的高级综合方法。该方法的一个基本特征是结构可测试性模型，该模型将可测试性作为一种结构设计风格集成到设计过程中。主要目标是开发一个系统级综合工具集，将行为描述映射到受用户定义约束的优化且可测试的RTL设计上。该方法涉及以下系统级迭代中的几个主要组件:调度和分配、约束估计和可测试性权衡。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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SYNTEST: a method for high-level SYNthesis with self-TESTability

The article introduces a new high-level synthesis method for self-testable RTL designs. A basic feature of this method is a structural testability model which treats testability as a structural design style integrated in the design process. The main objective is to develop a system-level synthesis tool set mapping a behavioral description onto an optimized and testable RTL design subject to user-defined constraints. The approach involves several major components within the following system-level iteration: scheduling and allocation, constraint estimation, and testability tradeoffs.<>

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[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

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