VLSI实现的一种新的分组密码

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI:10.1109/ICCD.1991.139960

H. Bonnenberg, A. Curiger, N. Felber, H. Kaeslin, Xuejia Lai

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引用次数: 28

摘要

提出了一种新型智能密钥分组密码的高速VLSI结构。该芯片在单个硬件单元中执行数据加密和解密。它以最大时钟频率33mhz运行，允许数据转换速率超过55mb /s。与目前可用的DES(数据加密标准)实现相比，这种高数据速率是通过实现流水线架构和使用复杂的数据调度方案来实现的，该方案保证了连续满负荷的管道。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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VLSI implementation of a new block cipher

The high speed architecture for a VLSI implementation of a new smart-key block cipher is presented. The chip performs data encryption and decryption in a single hardware unit. It runs with a maximum clock frequency of 33 MHz permitting a data conversion rate of more than 55 Mb/s. This high data rate, compared to currently available DES (data encryption standard) implementations, has been achieved by implementing a pipelined architecture and by using a sophisticated data scheduling scheme guaranteeing a continuously fully loaded pipeline.<>

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来源期刊

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

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