Robust path delay-fault testability on dynamic CMOS circuits

Abstract

The properties of delay-fault testability on dynamic CMOS logic circuits are investigated. It is demonstrated that the concepts of static sensitizability and robust path delay-fault (RPDF) testability are synonymous on these circuits, and that hence RPDF testability is somewhat easier on these circuits than on static logic circuits. It is also argued that a less restrictive testability condition than the RPDF criterion detects all path delay-faults which will affect the operation of the circuit. It is shown that the set of test vectors which satisfies this less-restrictive condition is exactly the union of the on-sets of the primary circuit outputs.<>