Modeling of interconnection lines for simulation of VLSI circuits

A modeling approach for RC delays of interconnection lines, based on a lumped resistor and capacitor ladder, for the distributed RC transmission line, is presented. The interconnection line is considered to be driven by a MOS gate source, MOS gate loads, and RC interconnection branches. The minimum number of required RC sections is obtained for each case of driving an interconnection line and for a specified average relative error. Also, a rule based on the worst case of driving an interconnection branch in a complex RC tree network is proposed in order to automatically determine the recommended number of RC sections. This can be used as a first step before timing simulations.<>