{"title":"一种生成高效模拟器的技术","authors":"P. Bakowski, J. Dubois, A. Pawlak","doi":"10.1109/ICCD.1991.139855","DOIUrl":null,"url":null,"abstract":"A methodology is presented aimed at reducing the size of generated simulators and at increasing their simulation speed. This technique consists in abstracting the functionality of an architecture's control part into a data table and mapping it onto the main memory of a host computer. The Lille University simulator called LIDO was used as a testbed for experiments. Some decision making capabilities of the generator based on static analysis of characteristics of an architecture and empirically refined are presented. Results of comparative tests with a VHDL simulator are discussed.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A technique for generating efficient simulators\",\"authors\":\"P. Bakowski, J. Dubois, A. Pawlak\",\"doi\":\"10.1109/ICCD.1991.139855\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A methodology is presented aimed at reducing the size of generated simulators and at increasing their simulation speed. This technique consists in abstracting the functionality of an architecture's control part into a data table and mapping it onto the main memory of a host computer. The Lille University simulator called LIDO was used as a testbed for experiments. Some decision making capabilities of the generator based on static analysis of characteristics of an architecture and empirically refined are presented. Results of comparative tests with a VHDL simulator are discussed.<<ETX>>\",\"PeriodicalId\":239827,\"journal\":{\"name\":\"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-10-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.1991.139855\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.1991.139855","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A methodology is presented aimed at reducing the size of generated simulators and at increasing their simulation speed. This technique consists in abstracting the functionality of an architecture's control part into a data table and mapping it onto the main memory of a host computer. The Lille University simulator called LIDO was used as a testbed for experiments. Some decision making capabilities of the generator based on static analysis of characteristics of an architecture and empirically refined are presented. Results of comparative tests with a VHDL simulator are discussed.<>