一种生成高效模拟器的技术

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI:10.1109/ICCD.1991.139855

P. Bakowski, J. Dubois, A. Pawlak

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引用次数: 0

摘要

提出了一种减小生成的仿真器尺寸和提高仿真速度的方法。该技术包括将体系结构控制部分的功能抽象为数据表，并将其映射到主机的主存储器上。里尔大学的模拟器LIDO被用作实验的试验台。通过对体系结构特征的静态分析和经验改进，给出了该生成器的一些决策能力。讨论了与VHDL模拟器的对比试验结果

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A technique for generating efficient simulators

A methodology is presented aimed at reducing the size of generated simulators and at increasing their simulation speed. This technique consists in abstracting the functionality of an architecture's control part into a data table and mapping it onto the main memory of a host computer. The Lille University simulator called LIDO was used as a testbed for experiments. Some decision making capabilities of the generator based on static analysis of characteristics of an architecture and empirically refined are presented. Results of comparative tests with a VHDL simulator are discussed.<>

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来源期刊

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

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