工程变更的增量综合

Yosinori Watanabe, R. Brayton
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引用次数: 40

摘要

阐述了超大规模集成电路由于规格变化引起的设计误差和设计误差的校正问题,并提出了一种利用逻辑综合技术的基本方法。提出了一种通过将电路外部附加到原设计上来纠正功能错误的有效方法。提出了全面整改设计的充分必要条件。结果表明,该方法在任意组合电路的整流中均能取得成功。简要回顾了在实际设计过程中出现整改的情况。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Incremental synthesis for engineering changes
The problem of rectifying design incorrectness due to specification changes as well as design errors of VLSI circuits is formulated and a basic approach using logic synthesis techniques is presented. An efficient approach is presented for rectifying the functional incorrectness by attaching circuitry exterior to the original design. A necessary and sufficient condition for full rectification of the design is provided. It is shown that the proposed approach always succeeds in the rectification of arbitrary combinational circuits. The situation where rectification arises in a practical design process is briefly reviewed.<>
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