数据流图的可访问性分析:一种可测试性设计方法

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI:10.1109/ICCD.1991.139948

Chung-Hsing Chen, Chienwen Wu, D. Saab

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引用次数: 11

摘要

增加内部电路节点的可访问性是实现可测试性设计的一种方法。提出了一种基于数据流图(DFG)的可达性分析算法。在此基础上，提出了提高总可达性的方法。这是通过选择需要可访问的最小电路节点集来实现的，以确保所有其他节点都可访问。对DFG进行了一个简单的修改，增加了可访问性。

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Accessibility analysis on data flow graph: an approach to design for testability

Increasing the accessibility of an internal circuit node is one way to achieve design for testability. An algorithm for accessibility analysis based on a data flow graph (DFG) is presented. Based on this analysis, an approach is proposed for improving total accessibility. This is accomplished by selecting the minimum set of circuit nodes that need to be made accessible to ensure that all other nodes are accessible. A simple modification to the DFG that increases accessibility is presented.<>

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[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

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