A fine grain architecture for parallel fault simulation

An architecture is presented for performing event-driven logic simulation using either unit or zero gate delay models. The architecture is based on a fine grain logic gate evaluation element which can simulate a single gate in a circuit. These simple elements can be implemented using VLSI and many such elements make up the simulation architecture. Each gate evaluation element can match a node identifier transmitted on a bus allowing the architecture to search fanout lists in one cycle. The gate evaluation element is designed with additional circuitry allowing it to save or restore the complete state of the machine in one cycle so it can support fault simulation using the concurrent and differential fault simulation algorithms.<>