用于最小化硬件开销的内置自我测试方法

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI:10.1109/ICCD.1991.139898

S. Chiu, C. Papachristou

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引用次数: 46

摘要

介绍了一种内置自检(BIST)硬件插入技术。该技术应用于寄存器传输电平设计，不仅利用了电路结构，而且利用了模块功能，减少了测试硬件开销。实验结果表明，与其他系统级BIST技术相比，该技术的面积开销减少了38%。

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A built-in self-testing approach for minimizing hardware overhead

A built-in self-test (BIST) hardware insertion technique is addressed. Applying to register transfer level designs, this technique utilizes not only the circuit structure but also the module functionality in reducing test hardware overhead. Experimental results have shown up to 38% reduction in area overhead over other system level BIST techniques.<>

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[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

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