冗余电路的随机可测试性

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors Pub Date : 1991-10-14 DOI:10.1109/ICCD.1991.139936

A. Krasniewski, A. Albicki

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引用次数: 4

摘要

结果表明，通常认为任何优化的，即非冗余的电路比其非优化的对应电路更容易测试的观点是不完全正确的。通过实例证明，冗余电路比优化后的冗余电路更适合随机测试。提出了一种规则，该规则规定了冗余何时可能增强两级与或门网络的随机可测试性。

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Random testability of redundant circuits

It is shown that the common belief that any optimized, i.e., nonredundant, circuit is easier to test than its nonoptimized counterpart is not fully justified. It is demonstrated by example that a redundant circuit may be more suitable for random testing than its optimized counterpart. A rule which specifies when redundancy is likely to enhance random testability of a two-level AND-OR gate network is formulated.<>

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[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors

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