Design methodology for a MIPS compatible embedded control processor

Abstract

The design methodology of a 700000-transistor, 50 MHz MIPS-1 compatible embedded control processor, the LR33000, is described. This single chip processor consists of an R3000-compatible CPU, 8 kB of instruction cache, 1 kB of data cache, a DRAM controller, write buffer, timers, and a programmable system interface which directly connects to DRAM, SRAM and PROM. A mix of synthesis and schematic entry, hand and automatic optimization was used for logic design. The short design time and bug-free first-run silicon have demonstrated the success of this design methodology.<>