Optimal clocking of circular pipelines

Abstract

A timing model for circular pipelines is presented and used to obtain the minimum cycle time in terms of circuit delays and clock skews. The model accounts for short- and long-path delays, the effects of clock skew, and the use of both latches and flip-flops as synchronizing elements. The formulation and implementation of algorithms to find the minimum cycle time for both single-phase and a restricted class of multi-phase clocks are described.<>