MIPS兼容嵌入式控制处理器的设计方法

Raymond Peck, Jay Patel
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引用次数: 2

摘要

介绍了一种70万晶体管、50 MHz兼容MIPS-1的嵌入式控制处理器LR33000的设计方法。该单片机由兼容r3000的CPU、8kb指令缓存、1kb数据缓存、DRAM控制器、写缓冲区、定时器和可编程系统接口组成,该接口可直接连接DRAM、SRAM和PROM。逻辑设计采用综合和原理图输入、手工优化和自动优化相结合的方法。短的设计时间和无bug的首次运行硅证明了这种设计方法的成功。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design methodology for a MIPS compatible embedded control processor
The design methodology of a 700000-transistor, 50 MHz MIPS-1 compatible embedded control processor, the LR33000, is described. This single chip processor consists of an R3000-compatible CPU, 8 kB of instruction cache, 1 kB of data cache, a DRAM controller, write buffer, timers, and a programmable system interface which directly connects to DRAM, SRAM and PROM. A mix of synthesis and schematic entry, hand and automatic optimization was used for logic design. The short design time and bug-free first-run silicon have demonstrated the success of this design methodology.<>
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