{"title":"MIPS兼容嵌入式控制处理器的设计方法","authors":"Raymond Peck, Jay Patel","doi":"10.1109/ICCD.1991.139909","DOIUrl":null,"url":null,"abstract":"The design methodology of a 700000-transistor, 50 MHz MIPS-1 compatible embedded control processor, the LR33000, is described. This single chip processor consists of an R3000-compatible CPU, 8 kB of instruction cache, 1 kB of data cache, a DRAM controller, write buffer, timers, and a programmable system interface which directly connects to DRAM, SRAM and PROM. A mix of synthesis and schematic entry, hand and automatic optimization was used for logic design. The short design time and bug-free first-run silicon have demonstrated the success of this design methodology.<<ETX>>","PeriodicalId":239827,"journal":{"name":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","volume":"59 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Design methodology for a MIPS compatible embedded control processor\",\"authors\":\"Raymond Peck, Jay Patel\",\"doi\":\"10.1109/ICCD.1991.139909\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design methodology of a 700000-transistor, 50 MHz MIPS-1 compatible embedded control processor, the LR33000, is described. This single chip processor consists of an R3000-compatible CPU, 8 kB of instruction cache, 1 kB of data cache, a DRAM controller, write buffer, timers, and a programmable system interface which directly connects to DRAM, SRAM and PROM. A mix of synthesis and schematic entry, hand and automatic optimization was used for logic design. The short design time and bug-free first-run silicon have demonstrated the success of this design methodology.<<ETX>>\",\"PeriodicalId\":239827,\"journal\":{\"name\":\"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors\",\"volume\":\"59 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-10-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.1991.139909\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.1991.139909","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design methodology for a MIPS compatible embedded control processor
The design methodology of a 700000-transistor, 50 MHz MIPS-1 compatible embedded control processor, the LR33000, is described. This single chip processor consists of an R3000-compatible CPU, 8 kB of instruction cache, 1 kB of data cache, a DRAM controller, write buffer, timers, and a programmable system interface which directly connects to DRAM, SRAM and PROM. A mix of synthesis and schematic entry, hand and automatic optimization was used for logic design. The short design time and bug-free first-run silicon have demonstrated the success of this design methodology.<>