Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)最新文献

{"title":"Scan-path with directly duplicated and inverted duplicated registers","authors":"M. Gössel, E. Sogomonyan, A. Singh","doi":"10.1109/VTS.2002.1011110","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011110","url":null,"abstract":"In this paper a systematic scan-path design with duplicated and inverted duplicated memory elements is proposed. Contrary to a known solution (Raina et al., 2000), no additional control lines for additional multiplexors are needed. Full controllability and observability of the proposed scan-path is demonstrated.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116057893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Software-based weighted random testing for IP cores in bus-based programmable SoCs","authors":"Madhu K. Iyer, K. Cheng","doi":"10.1109/VTS.2002.1011125","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011125","url":null,"abstract":"Presents a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition probabilities (profiles) at the inputs of circuits with full-scan using testability metrics based on the targeted fault model, We use a genetic algorithm (GA) based search procedure to determine optimal profiles. We use these optimal profiles to generate a test program that runs on the processor core. This program applies test patterns to the target IP cores in the SoC and analyzes the test responses. This provides the flexibility of applying multiple profiles to the IP core under test to maximize fault coverage. This scheme does not incur the hardware overhead of logic BIST, since the pattern generation and analysis is done by software. We use a probabilistic approach to finding the profiles. We describe our method on transition and path-delay fault models, for both enhanced full-scan and normal full-scan circuits. We present experimental results using the ISCAS 89 benchmarks as IP cores.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124477932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits","authors":"Toshinori Hosokawa, H. Date, M. Muraoka","doi":"10.1109/VTS.2002.1011161","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011161","url":null,"abstract":"This paper proposes a test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits with DFT where hierarchical test generations are applicable. Moreover, a heuristic algorithm for a compacted test plan table generation is proposed. The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131387505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved test monitor circuit in power pin DfT","authors":"R. Schuttert, F. Jong, B. Kup","doi":"10.1109/VTS.2002.1011163","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011163","url":null,"abstract":"The power pin monitor cell developed by Philips was a significant step in solving the problem of detecting open power pins in paralleled power pin IC designs. This paper present an improved monitor cell design that provides better detection and it is further enhanced by the addition of an improved boundary scan control mechanism. Extensive trials confirm the cell performance and the presented results are analysed and discussed The cells were observed and controlled using an IEEE Std 1149.1 TAP controller.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128204372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An efficient test relaxation technique for combinational & full-scan sequential circuits","authors":"A. El-Maleh, Ali Al-Suwaiyan","doi":"10.1109/VTS.2002.1011111","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011111","url":null,"abstract":"Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper we propose a novel and efficient test relaxation technique for combinational and full-scan sequential circuits. The proposed technique is faster than the brute-force test relaxation method by several orders of magnitude. The application of the technique in improving the effectiveness of test compaction and compression is illustrated.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130385864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SoCs with MEMS? Can we include MEMS in the SoCs design and test flow?","authors":"S. Mir, H. Bederr, R. D. Blanton, H. Kerkhoff, H. J. Klim","doi":"10.1109/VTS.2002.1011179","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011179","url":null,"abstract":"Position Statement S. Mir : MEMS are analog components. Embedding them in highly integrated devices means new test challenges for the analog and mixed-signal test community due to the multiple energy domains considered. Failure mechanisms and reliability are poorly understood and structured test approaches are generally missing. Functional testing of MEMS parts may be unavoidable, together with the use of expensive test equipment able to deal with signals other than electrical. Extremely high test costs together with poor reliability of MEMS blocks are major obstacles to see this type of cores in the SoCs of the near future. Position Statement H. Kerkhoff : Firstly, in contrast to conventional microelectronics and current SoC, many MEM device specifications are quite dependent on the final packaging implementation, as this determines the interaction between the actual domain and the electronic voltage or current and vice versa. Hence, models of MEMS in which the influence of packaging is not or partially included will therefore not be sufficiently accurate to be used in practice. This will involve much additional research, and data to be given by core providers. As a result, designers will probably be forced to use predetermined (and modeled) packages for these devices, which will be a new issue in SoC design and test. Secondly, in many cases, for several parts of MEMS (e.g. mechanical valves) it will not be feasible to develop a direct test in a mass-production environment, unless full functional tests are allowed. In this case, special Design-for-Test structures should be included in the MEMS to transform non-electrical properties into electrical ones, e.g. via capacitances (movement to electrical property). These should be part of the data given by core providers as well as standards for MEM tests. Position Statement S. Blanton : Are new testing methodologies and tools needed for SoCs with MEMS? The answer is unquestionably \"yes\". MEMS, in the most general sense, are sophisticated, miniature transducers that convert one type of energy (mechanical, thermal, optical, etc.) to another type (typically electrical) or vice-versa. Maximally testing MEMS in an all electrical domain would allow existing tester hardware to be utilized. Unfortunately, this is not possible given the mixed-physics properties of MEMS. For example, accelerometers must be literally \"shaken\" to provide the mechanical input stimulus needed to test and calibrate the interface between the mechanical and electrical components. Similarly, the test of other MEMS will requi re non-electrical stimulus generators and output response analyzers in order to test and assess their behavior. In addition, any attempts to implement MEMS structural test will require an understanding of the defect types and consequent misbehaviors. It is unlikely that this understanding will stem from an extrapolation of the defect types found in purely electronic systems. Moreover, the defect types will most li","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129833851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluation of effectiveness of median of absolute deviations outlier rejection-based I/sub DDQ/ testing for burn-in reduction","authors":"S. Sabade, D. Walker","doi":"10.1109/VTS.2002.1011115","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011115","url":null,"abstract":"CMOS chips having high leakage are observed to have high burn-in fallout rate. I/sub DDQ/ testing has been considered as an alternative to burn-in. However, increased subthreshold leakage current in deep submicron technologies limits the use of I/sub DDQ/ testing in its present form. In this work, a statistical outlier rejection technique known as the median of absolute deviations (MAD) is evaluated as a means to screen early failures using I/sub DDQ/ data. MAD is compared with delta I/sub DDQ/ and current signature methods. The results of the analysis of the SEMATECH data are presented.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131029975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Test vector compression using EDA-ATE synergies","authors":"A. Khoche, Erik H. Volkerink, J. Rivoir, S. Mitra","doi":"10.1109/VTS.2002.1011118","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011118","url":null,"abstract":"This paper presents a new test vector compression technique, which utilizes synergies between Automatic Test Pattern Generation (ATPG) tools provided by EDA (Electronic Design Automation) vendors and Automatic Test Equipment (ATE). The basic approach is to achieve significant compression by agreeing between ATE and ATPG on how to fill don't care values in the test vectors such that these bits need not be stored on ATE and also possibly not communicated to DUT if decompression is done on chip. Our new technique allows sub-vector level fine grained mixing of pseudo-randomly generated bits and ATPG generated bits. Experimental results, on an actual industrial network processor design, show a compression ratio of about 17x.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133281475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Statistical post-processing at wafersort-an alternative to burn-in and a manufacturable solution to test limit setting for sub-micron technologies","authors":"R. Madge, Manu Rehani, Kevin Cota, W. R. Daasch","doi":"10.1109/VTS.2002.1011113","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011113","url":null,"abstract":"In sub-micron CMOS processes, it has become increasingly difficult to identify and separate outliers from the intrinsic distribution at test. This is due to the increasing inadequacy of reliability screens such as burn-in and IDDQ testing. Statistical Post-Processing (SPP) methods have been developed to run off-tester using the raw data generated from Automatic Test Equipment (ATE) and wafersort maps. Post-Processing modules include advanced IDDQ tests such as Delta IDDQ and the Nearest Neighbor Residual (NNR), as well as other non-IDDQ based reliability-focused modules. This work presents the application and results of SPP at LSI Logic on 0.18 /spl mu/m CMOS products. Challenges of production implementation have been overcome, which include \"user definable\" adaptive threshold limits, handling multiple data sources, and data flow management. Burn-in data and customer Defects per Million units (DPM) data show a 30-60% decrease in failure rate with SPP implementation with very acceptable yield loss.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134206910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On using efficient test sequences for BIST","authors":"R. David, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel","doi":"10.1109/VTS.2002.1011126","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011126","url":null,"abstract":"High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134478621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}