Improved test monitor circuit in power pin DfT

Abstract

The power pin monitor cell developed by Philips was a significant step in solving the problem of detecting open power pins in paralleled power pin IC designs. This paper present an improved monitor cell design that provides better detection and it is further enhanced by the addition of an improved boundary scan control mechanism. Extensive trials confirm the cell performance and the presented results are analysed and discussed The cells were observed and controlled using an IEEE Std 1149.1 TAP controller.