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Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)最新文献

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Test hardware design challenges in RF testing 测试硬件设计在射频测试中的挑战
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-08-07 DOI: 10.1109/VTS.2002.1011130
M. Slamani, H. Ding
{"title":"Test hardware design challenges in RF testing","authors":"M. Slamani, H. Ding","doi":"10.1109/VTS.2002.1011130","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011130","url":null,"abstract":"","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132681350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Open problems in wireless test and why you should care 无线测试中存在的问题及应注意的原因
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-08-07 DOI: 10.1109/VTS.2002.1011132
J. McLaughlin
{"title":"Open problems in wireless test and why you should care","authors":"J. McLaughlin","doi":"10.1109/VTS.2002.1011132","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011132","url":null,"abstract":"","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122736391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Timed test generation for crosstalk switch failures in domino CMOS 多米诺CMOS串扰开关故障的定时测试生成
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-08-07 DOI: 10.1109/VTS.2002.1011168
R. Kundu, R. D. Blanton
{"title":"Timed test generation for crosstalk switch failures in domino CMOS","authors":"R. Kundu, R. D. Blanton","doi":"10.1109/VTS.2002.1011168","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011168","url":null,"abstract":"As technology scales into the deep submicron regime, capacitive coupling between signal lines becomes a dominant problem. Capacitive coupling is more acute for domino logic circuits since an irreversible, unwanted gate output transition can result. We present a timed test generation methodology for CMOS domino circuits that assigns the circuit inputs so that capacitively-coupled aggressors of a victim line transition in time proximity which creates a noise effect that is propagated within the clock-cycle constraint. Experiments for a multiplier reveal that a high level of accuracy is achieved without significant test generation time, resulting in a nearly 50% reduction in the number of sites earlier believed to be susceptible to crosstalk failure.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116047998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Programmable embedded IF source for wireless test 可编程嵌入式中频源无线测试
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-08-07 DOI: 10.1109/VTS.2002.1011131
W. Eisenstadt, Sanghoon Choi
{"title":"Programmable embedded IF source for wireless test","authors":"W. Eisenstadt, Sanghoon Choi","doi":"10.1109/VTS.2002.1011131","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011131","url":null,"abstract":"","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"87 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128849929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Layout analysis to extract open nets caused by systematic failure mechanisms 布置图分析，提取开网引起系统失效的机理
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011166
S. Chakravarty, K. Komeyli, Eric W. Savage, Michael J. Carruthers, Bret T. Stastny, S. Zachariah
{"title":"Layout analysis to extract open nets caused by systematic failure mechanisms","authors":"S. Chakravarty, K. Komeyli, Eric W. Savage, Michael J. Carruthers, Bret T. Stastny, S. Zachariah","doi":"10.1109/VTS.2002.1011166","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011166","url":null,"abstract":"Previously published work has pointed out that open defects are escaping test screens. To plug this hole, tests directed at nets susceptible to opens are required, and, therefore, nets susceptible to opens need to be identified. Opens caused by random particles have been modeled using weighted critical area (WCA) and have been previously studied. Here, we present a model that abstracts a class of systematic failure mechanisms that leads to open nets. An algorithm to calculate net scores using this model is presented. Experimental results on industrial designs show the algorithm to have reasonable performance.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"102 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123166666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An industrial environment for high-level fault-tolerant structures insertion and validation 用于高级容错结构插入和验证的工业环境
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011143
L. Berrojo, Isabel González, Fulvio Corno, M. Reorda, Giovanni Squillero, L. Entrena, C. López-Ongil
{"title":"An industrial environment for high-level fault-tolerant structures insertion and validation","authors":"L. Berrojo, Isabel González, Fulvio Corno, M. Reorda, Giovanni Squillero, L. Entrena, C. López-Ongil","doi":"10.1109/VTS.2002.1011143","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011143","url":null,"abstract":"When designing a VLSI circuits, most of the efforts are now performed at levels of abstractions higher than gate. Correspondingly to this clear trend, there is a growing request to tackle safety-critical issues directly at the RT-level. This paper presents a complete environment for considering safety issues at the RT level. The environment was implemented and tested by an industry for devising a sample safety-critical device. Designers were permitted to assess the effects of transient faults, automatically add fault-tolerant structures, and validate the results working on the same circuit descriptions and acting in a coherent framework. The evaluation showed the effectiveness of the proposed environment.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116646109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Filters designed for testability wrapped on the Mixed-Signal Test Bus 滤波器设计用于封装在混合信号测试总线上的可测试性
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011139
J. Calvano, V. Alves, A. C. M. Filho, M. Lubaszewski
{"title":"Filters designed for testability wrapped on the Mixed-Signal Test Bus","authors":"J. Calvano, V. Alves, A. C. M. Filho, M. Lubaszewski","doi":"10.1109/VTS.2002.1011139","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011139","url":null,"abstract":"This work presents a design for test method for continuous time active filters of any order, using the IEEE 1149.4 as its backbone structure. The method relies on the synthesis of filter transfer functions using partial fraction extraction. Transfer functions are built from 1/sup st/ order blocks connected via the available standard infrastructure. Under this approach, structural test can be carried out using simple test vectors, which are disclosed according to a fault simulation process.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123407222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Useless memory allocation in system-on-a-chip test: problems and solutions 片上系统测试中无用的内存分配:问题与解决方法
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011175
P. T. Gonciari, B. Al-Hashimi, N. Nicolici
{"title":"Useless memory allocation in system-on-a-chip test: problems and solutions","authors":"P. T. Gonciari, B. Al-Hashimi, N. Nicolici","doi":"10.1109/VTS.2002.1011175","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011175","url":null,"abstract":"Unlike the existing research direction that focuses on useful test data reduction, this paper analyzes the useless test data memory requirements for system-on-a-chip test. The proposed solution to minimize the useless test memory is based on a new test methodology which combines a novel core wrapper design algorithm with a new test vector deployment procedure stored in the automatic test equipment (ATE). To reduce memory requirements, the proposed core wrapper design finds the minimum number of wrapper scan chain partitions such that the useless memory allocation is minimized in each partition, which facilitates efficient usage of ATE capabilities. Further the new test vector deployment procedure provides a seamless integration with the ATE. When compared to the previously proposed core wrapper design algorithms, the proposed test methodology reduces the memory requirements up to 45%, without any penalties in test area overhead.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129032713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Fault models for speed failures caused by bridges and opens 桥梁和开口引起的速度故障的故障模型
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011167
S. Chakravarty, Ankur Jain
{"title":"Fault models for speed failures caused by bridges and opens","authors":"S. Chakravarty, Ankur Jain","doi":"10.1109/VTS.2002.1011167","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011167","url":null,"abstract":"A number of new transition fault models for resistive vias and contacts in static CMOS circuits that cause speed failures are presented. The uniqueness of the new fault models are formally established. Fault simulation experiments performed on a large microprocessor show that there is no correlation between the newly proposed models and the classical fault models. Finally, we show that failures caused by bridges and opens in domino CMOS circuits require different fault models, and different test application considerations, than static CMOS circuits. It shows that there are defects that do not cause errors when tests are applied at high speed but fail when tests are applied at slow speed. This contradicts an assumption often made in speed-binning.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126528181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Evaluation of the oscillation-based test methodology for micro-electro-mechanical systems 微机电系统振荡试验方法的评价
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011177
V. Beroulle, Y. Bertrand, L. Latorre, P. Nouet
{"title":"Evaluation of the oscillation-based test methodology for micro-electro-mechanical systems","authors":"V. Beroulle, Y. Bertrand, L. Latorre, P. Nouet","doi":"10.1109/VTS.2002.1011177","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011177","url":null,"abstract":"In this paper, Oscillation-based Test Methodology (OTM) is evaluated in the context of MEMS testing. Both qualitative and quantitative evaluations of fault coverage are discussed and the impact of test on production yield is addressed. This article also introduces the Lorentz force as a low-cost stimulus for electro-mechanical structures.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121762032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
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