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Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)最新文献

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Controlling peak power during scan testing 控制扫描测试时的峰值功率
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011127
Ranganathan Sankaralingam, N. Touba
{"title":"Controlling peak power during scan testing","authors":"Ranganathan Sankaralingam, N. Touba","doi":"10.1109/VTS.2002.1011127","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011127","url":null,"abstract":"This paper presents a procedure for modifying a given set of scan vectors so that the peak power during scan testing is kept below a specified limit without reducing fault coverage. The proposed approach works for any conventional full-scan design-no extra design-for-test (DFT) logic is required. If the peak power in a clock cycle during scan testing exceeds a specified limit (which depends on the amount of peak power that can be safely handled without causing a failure that would not occur during normal functional operation) then a \"peak power violation\" occurs. Given a set of scan vectors, simulation is done to identify and classify the scan vectors that are causing peak power violations during scan testing. The problem scan vectors are then modified in a way that eliminates the peak power violations while preserving the fault coverage. Experimental results indicate the proposed procedure is very effective in controlling peak power.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131497455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 115
Program slicing for hierarchical test generation 分层测试生成的程序切片
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011144
V. Vedula, J. Abraham, J. Bhadra
{"title":"Program slicing for hierarchical test generation","authors":"V. Vedula, J. Abraham, J. Bhadra","doi":"10.1109/VTS.2002.1011144","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011144","url":null,"abstract":"Sequential Automatic Test Pattern Generation (ATPG) is extremely computation intensive and produces good results only on relatively small designs. This paper develops an elegant theoretical basis, based on program slicing, for hierarchical ATPG which targets one module at a time and abstracts the rest of the design. The technique for obtaining a \"constraint slice\" for each embedded Module Under Test (MUT) within a design is described in detail. The technique has been incorporated in an automated tool for designs described in Verilog, and results on large benchmark circuits show the significant benefits of the approach.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133428079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Speeding up the Byzantine fault diagnosis using symbolic simulation 利用符号仿真加速拜占庭式故障诊断
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011138
Shi-Yu Huang
{"title":"Speeding up the Byzantine fault diagnosis using symbolic simulation","authors":"Shi-Yu Huang","doi":"10.1109/VTS.2002.1011138","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011138","url":null,"abstract":"Fault diagnosis is to predict the potential fault sites in a logic IC. In this paper, we particularly address the problem of diagnosing faults that exhibit the so-called Byzantine General's phenomenon, in which a fault manifests itself as a non-logical voltage level at the fault site. Previously, explicit enumeration was suggested to deal with such a problem. However, it is often too time-consuming because the CPU time is exponentially proportional to fanout degree of the circuit under diagnosis. To speed up this process, we present an implicit enumeration technique using symbolic simulation. Experimental results show that the CPU time can be improved by several orders of magnitude for ISCAS85 benchmark circuits.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133032522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
Timing jitter measurement of 10 Gbps bit clock signals using frequency division 使用分频测量10gbps位时钟信号的时序抖动
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011140
Takahiro J. Yamaguchi, M. Ishida, M. Soma, Louis Malarsie, H. Musha
{"title":"Timing jitter measurement of 10 Gbps bit clock signals using frequency division","authors":"Takahiro J. Yamaguchi, M. Ishida, M. Soma, Louis Malarsie, H. Musha","doi":"10.1109/VTS.2002.1011140","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011140","url":null,"abstract":"This paper presents a new method for measuring timing jitter of the bit clock signal in telecommunication devices operating at 10 Gbps. The method uses a divide-by-M circuit to reduce the frequency and the number of clock samples, and applies the Hilbert transform to measure the timing jitter The theory for this frequency division method is supported by the experimental data from a serializer-deserializer device.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122408087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Yield-reliability modeling: experimental verification and application to burn-in reduction 产量可靠性模型:实验验证及在减少磨损上的应用
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011114
T. S. Barnett, A. Singh, M. Grady, Kathleen G. Purdy
{"title":"Yield-reliability modeling: experimental verification and application to burn-in reduction","authors":"T. S. Barnett, A. Singh, M. Grady, Kathleen G. Purdy","doi":"10.1109/VTS.2002.1011114","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011114","url":null,"abstract":"An integrated yield-reliability model is verified using burn-in data from 77,000 microprocessor units manufactured by IBM Microelectronics. The model is based on the fact that defects over semiconductor wafers are not randomly distributed, but have a tendency to cluster. It is shown that this fact can be exploited to produce die of varying reliability by sorting die into bins based on how many of their neighbors test faulty. Die that test good at wafer probe, yet come from regions with many faulty die, have a higher incidence of infant mortality failure than die from regions with few faulty die. The yield-reliability model is used to predict the fraction of good die in each bin following wafer probing as well as the fraction of failures in each bin following stress testing (e.g. burn-in). Results show excellent agreement between model predictions and observed data.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122877549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Self-testing second-order delta-sigma modulators using digital stimulus 利用数字刺激自测二阶δ - σ调制器
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 1900-01-01 DOI: 10.1109/vts.2002.1011122
Chee-Kian Ong, Kwang-Ting Cheng
{"title":"Self-testing second-order delta-sigma modulators using digital stimulus","authors":"Chee-Kian Ong, Kwang-Ting Cheng","doi":"10.1109/vts.2002.1011122","DOIUrl":"https://doi.org/10.1109/vts.2002.1011122","url":null,"abstract":"","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116302787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) 第二十届IEEE VLSI测试研讨会论文集(VTS 2002)
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 1900-01-01 DOI: 10.1109/VTS.2002.1011102
{"title":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","authors":"","doi":"10.1109/VTS.2002.1011102","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011102","url":null,"abstract":"The following topics are dealt with: microprocessor test; very low voltage testing; DFT testers; test set compression techniques; analog BIST; slow speed testing; test automation; scan-based testing; burn-in reduction; test power; fault diagnosis; analog circuit testing; high level test techniques; SoC test; supply current testing; IEEE P1500; test pattern generation; tester hardware modelling; FPGA test; fault modeling; memory testing; test-cost reduction; and oscillation based test.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122612833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
RAMSES-FT: a fault simulator for flash memory testing and diagnostics RAMSES-FT:用于闪存测试和诊断的故障模拟器
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 1900-01-01 DOI: 10.1109/vts.2002.1011153
Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
{"title":"RAMSES-FT: a fault simulator for flash memory testing and diagnostics","authors":"Kuo-Liang Cheng, Jen-Chieh Yeh, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu","doi":"10.1109/vts.2002.1011153","DOIUrl":"https://doi.org/10.1109/vts.2002.1011153","url":null,"abstract":"","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115982809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
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