Takahiro J. Yamaguchi, M. Ishida, M. Soma, Louis Malarsie, H. Musha
{"title":"使用分频测量10gbps位时钟信号的时序抖动","authors":"Takahiro J. Yamaguchi, M. Ishida, M. Soma, Louis Malarsie, H. Musha","doi":"10.1109/VTS.2002.1011140","DOIUrl":null,"url":null,"abstract":"This paper presents a new method for measuring timing jitter of the bit clock signal in telecommunication devices operating at 10 Gbps. The method uses a divide-by-M circuit to reduce the frequency and the number of clock samples, and applies the Hilbert transform to measure the timing jitter The theory for this frequency division method is supported by the experimental data from a serializer-deserializer device.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Timing jitter measurement of 10 Gbps bit clock signals using frequency division\",\"authors\":\"Takahiro J. Yamaguchi, M. Ishida, M. Soma, Louis Malarsie, H. Musha\",\"doi\":\"10.1109/VTS.2002.1011140\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new method for measuring timing jitter of the bit clock signal in telecommunication devices operating at 10 Gbps. The method uses a divide-by-M circuit to reduce the frequency and the number of clock samples, and applies the Hilbert transform to measure the timing jitter The theory for this frequency division method is supported by the experimental data from a serializer-deserializer device.\",\"PeriodicalId\":237007,\"journal\":{\"name\":\"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-04-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTS.2002.1011140\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTS.2002.1011140","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Timing jitter measurement of 10 Gbps bit clock signals using frequency division
This paper presents a new method for measuring timing jitter of the bit clock signal in telecommunication devices operating at 10 Gbps. The method uses a divide-by-M circuit to reduce the frequency and the number of clock samples, and applies the Hilbert transform to measure the timing jitter The theory for this frequency division method is supported by the experimental data from a serializer-deserializer device.