Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)最新文献

{"title":"Beyond CMOS","authors":"B. Courtoi, M. Forshaw","doi":"10.1109/VTS.2002.1011159","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011159","url":null,"abstract":"The slow but inevitable approach of the technological limit to CMOS has produced a steady increase in research into alternative or complementary devices and technologies. There is a wide spread in the maturity of this research and development, starting with relatively mature technologies such as MRAM or resonant tunneling diodes and rapid single flux quanta (RSFQ) systems. More speculative prospects include single-walled carbon nanotube (SWCNT) transistors and logic gates and the even more speculative molecular transistor devices. On an even longer timescale there hovers the prospect of quantum computing systems. It is important to try to assess the chances of any of these device technologies ever taking over from CMOS. The author discusses the problems these devices face. Additionally, all of the increasing research into nanoelectronics is helping to clarify which devices might or might not work. The study of nanoscale phenomena will help with the development of more robust devices and systems. More fundamental is the fact that there is still much room for manouver in nanoscale and mesoscale device technology: Examples will be presented to show how this design flexibility can be exploited.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127127129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Testing and diagnosing embedded content addressable memories","authors":"Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu","doi":"10.1109/VTS.2002.1011169","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011169","url":null,"abstract":"Embedded content addressable memories (CAMs) are important components in many system chips. In this paper two efficient March-like test algorithms are proposed. In addition to typical RAM faults, they also cover CAM-specific comparison faults. The first algorithm requires 9N Read/Write operations and 2(N+W) Compare operations to cover comparison and RAM faults (but does not fully cover the intra-word coupling faults), for an N/spl times/W-bit CAM. The second algorithm uses 3N log/sub 2/ W Write and 2W log/sub 2/ W Compare operations to cover the remaining intra-word coupling faults. Compared with the previous algorithms, the proposed algorithms have higher fault coverage and lower time complexity. Moreover it can test the CAM even when its comparison result is observed only by the Hit output or the priority encoder output. Fault-location algorithms are also developed for locating the cells with comparison faults.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129778272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A successful DFT tester: what will it look like? is revolution in test approaches required?","authors":"Lee Song, R. Garcia, A. Levy, D. L. Wheater","doi":"10.1109/VTS.2002.1011116","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011116","url":null,"abstract":"For many years, the semiconductor industry has been predicting the emergence of DFT tester market, enabled by increasing number of devices being designed with DFT methodologies such as scan and BIST. The search for low cost DFT tester solutions has resulted in the first ITRS roadmap for a DFT tester in 1999 and a major revision of this roadmap in 2001. While it is generally understood that a DFT tester can be used to limit the digital test performance envelope in production testing, some trends in the industry, such as increase in mixed signal SOC designs and multi GHz serial IO interfaces, may be pushing the industry toward more highly configurable and higher performance test solutions. The relative immaturity of analog mixed signal DFT, coupled with increasing proliferation of mixed signal SOC devices, may also prevent the wholesale industry-wide adoption of digital-only DFT testers. In addition, the emergence of novel fault models, beyond the traditional SSA model, to cover the emerging defects found in advanced silicon technologies have been noticeably lacking. Adding to the fire has been continuing discussion of the now famous $200/pin tester, which highlights the pressure faced by ATE companies in looking for a viable business model that can provide both high performance and low cost DFT testers at the same time. The result of this cloudiness in the industry has been relative slowness in the development of DFT testers by the ATE industry. However, the fact that adoption of DFT in devices is continuing leads us to believe that a DFT tester market will emerge eventually. The question is what kinds of DFT testers can best exploit the opportunities presented in this cloudy market. This is the first of two sessions that will explore various approaches in DFT tester development, features that may determine the success of DFT testers, and potential catalysts that may cause wide-scale industry adoption of DFT testers. This session explores whether successful DFT testers will take revolutionary departures from current mainstream testers.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124473582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Eigen-signatures for regularity-based IDDQ testing","authors":"Y. Okuda","doi":"10.1109/VTS.2002.1011155","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011155","url":null,"abstract":"Researchers and test engineers challenge I/sub DDQ/ testing on deep submicron (DSM) devices. We have proposed to test devices with high I/sub DDQ/ currents at normal operating conditions based on exploiting the regularity of defect-free I/sub DDQ/ signatures, the I/sub DDQ/ responses of a circuit on a test vector set. This paper demonstrates the fundamental characteristics of the regularity and proposes a new methodology based on eigen-signatures. Eigen-signatures are unique signatures transformed from I/sub DDQ/ signatures. The analysis of five eigen-signatures, including enhanced \"Delta I/sub DDQ/\" and \"Current Ratios,\" on a product indicates that: the I/sub DDQ/ values related to a test vector set have a small variation, whereas, the I/sub DDQ/ magnitudes have a large variation; and the defect current prediction error of methods focusing the changes between the test vectors is 23 times smaller than the error of methods focusing the I/sub DDQ/ magnitudes.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131125286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Logic BIST and scan test techniques for multiple identical blocks","authors":"Karim Arabi","doi":"10.1109/VTS.2002.1011112","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011112","url":null,"abstract":"In multi-million gate devices, the number of required test patterns may be beyond the limits of current external automatic test equipment (ATE) capabilities. Besides, excessive number of production test vectors results in prohibitive test time that increases the test cost and decreases the production capacity. This paper introduces a new technique to test multiple identical blocks in parallel. The proposed technique can be used either in conjunction with ATE or as a stand-alone BIST technique to test multiple identical blocks on the same chip. The test time and the number of test patterns for testing multiple blocks is only a little bit higher than what is required for testing one block.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123722037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Test pattern generation for signal integrity faults on long interconnects","authors":"A. Attarha, M. Nourani","doi":"10.1109/VTS.2002.1011162","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011162","url":null,"abstract":"In this paper we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and parasitic RLC elements of the interconnect. To enhance the performance of test generation process, model order reduction methodology is employed. This strategy significantly improves the simulation time with slight loss of accuracy.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116315674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Practical solutions for the application of the oscillation-based-test: start-up and on-chip evaluation","authors":"D. Vázquez, G. Huertas, G. Léger, A. Rueda, J. Huertas","doi":"10.1109/VTS.2002.1011176","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011176","url":null,"abstract":"This paper presents practical solutions for two of the main topics arising when applying oscillation-based-test: the start-up of the configured oscillator and the on-chip evaluation of the generated test signals. The required circuitry is very simple and robust. Moreover, preliminary results obtained from an integrated prototype are also included.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122762314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploiting dominance and equivalence using fault tuples","authors":"K. N. Dwarakanath, R. D. Blanton","doi":"10.1109/VTS.2002.1011151","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011151","url":null,"abstract":"Local dominance and equivalence relationships for a single fault type have been exploited to reduce test set size and test generation time. However, these relationships have not been explored for multiple fault types. Using fault tuples, we describe how local dominance and equivalence relationships across various fault types can be derived. We also describe how the derived relationships can be used to order the faults efficiently for test generation in order to reduce test set size. Initial results using our ordered fault lists for ISCAS85 and ITC99 benchmark circuits reveals that test set size can be reduced by as much as 19%.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117211278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Testing high-speed SoCs using low-speed ATEs","authors":"M. Nourani, J. Chin","doi":"10.1109/VTS.2002.1011124","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011124","url":null,"abstract":"Presents a test methodology to allow testing high-speed circuits with low-speed ATEs. The basic strategy is adding an interface circuit to partially supply test data, coordinate sending the test patterns and collecting the signatures. An ILP formulation is presented to globally optimize such coordination in terms of the overall test time and the hardware cost.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122197525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dynamic supply current testing of analog circuits using wavelet transform","authors":"S. Bhunia, K. Roy","doi":"10.1109/VTS.2002.1011158","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011158","url":null,"abstract":"Dynamic supply current (IDD) analysis has emerged as an effective way for defect oriented testing of analog circuits. In this paper, we propose using wavelet decomposition of IDD for fault detection in analog circuits. Wavelet transform has the property of resolving events in both time and frequency domain simultaneously unlike Fourier expansion which localizes a signal in terms of frequency only. Wavelet transform also has better sub-banding property and it can be easily adapted to current waveforms from different circuits. These make wavelet a more suitable candidate for fault detection in analog circuits than pure time-domain or pure frequency-domain methods. We have shown that for equivalent number of spectral components, sensitivity of wavelet based fault detection is much higher than Fourier or time-domain analysis for both catastrophic and parametric faults. Simulation results on benchmark circuits show that wavelet based method is on average 25 times more sensitive than DFT (Discrete Fourier Transform) for parametric faults and can be considered as a promising alternative for analog fault detection amidst measurement hardware noise and process variation.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114140590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}