Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)最新文献

{"title":"Design for testability and testing of IEEE 1149.1 TAP controller","authors":"S. Mitra, E. McCluskey, S. Makar","doi":"10.1109/VTS.2002.1011145","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011145","url":null,"abstract":"The Test Access Port (TAP) controller is a very important circuit present in all IC chips that are compliant with the IEEE 1149.1 Boundary Scan standard. Although the main purpose of boundary scan is to facilitate board-level testing, it is also used for many other testing and non-testing purposes (e.g., memory and logic BIST wrappers to enable embedded core test, programming FPGAs, checkpointing and recovery of dependable systems, etc.). Hence, it is important to thoroughly test the TAP controller before using it for other purposes. In this paper, we present techniques for designing and testing the TAP controller. Our design techniques simplify the procedure to test the TAP controller by orders of magnitude compared to previously published results. Our TAP controller design technique does not require any extra I/O pins and can be easily automated and incorporated into test tools.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121493120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reconfiguration technique for reducing test time and test data volume in Illinois Scan Architecture based designs","authors":"Amit R. Pandey, J. Patel","doi":"10.1109/VTS.2002.1011104","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011104","url":null,"abstract":"As the complexity of VLSI circuits is increasing due to the exponential rise in transistor count per chip, testing cost is becoming an important factor in the overall integrated circuit (IC) manufacturing cost. This paper addresses the issue of decreasing test cost by lowering the test data bits and the number of clock cycles required to test a chip. We propose a technique based on the reconfiguration of scan chains to reduce test time and test data volume for Illinois Scan Architecture (ILS) based designs. This technique is presented with details of hardware implementation as well as the test generation and test application procedures. The reduction in test time and test data volume achieved using this technique is quite significant in most circuits.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115031799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Is state mapping essential for equivalence checking custom memories in scan-based designs?","authors":"N. Krishnamurthy, J. Bhadra, M. Abadir, J. Abraham","doi":"10.1109/VTS.2002.1011152","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011152","url":null,"abstract":"Equivalence checking between Register Transfer Level (RTL) descriptions and transistor level descriptions of custom memories is an important step in the design flow of high performance microprocessors. Equivalence checking can be done with or without the knowledge of state mapping between the two descriptions. We present evidence that because of state mapping, our verification technique exercises system behavior that exposes hard-to-detect bugs that might otherwise go undetected. This paper defines Crossover Bugs (CB's) that can be present in scan-based custom designs and that are inherently hard-to-detect without state mapping. We demonstrate that such bugs can be missed by equivalence checking techniques that do not have state mappings between the two descriptions. By identifying the state correspondences between the RTL and the transistor implementation of custom memories, a more rigorous equivalence check can be performed compared to traditional equivalence checking methods such as product machine constructions. We also compare the time and memory complexities of crossover bug detection capability of the two equivalence checking approaches. We conclude with experimental results of CB detection on some of the custom designed embedded memories of Motorola's MPC 7455 microprocessor (compliant with IBM's PowerPC instruction set architecture).","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"526 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123064408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cluster-based test architecture design for system-on-chip","authors":"S. Goel, E. Marinissen","doi":"10.1109/VTS.2002.1011147","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011147","url":null,"abstract":"A test architecture for an SOC consists of a number of Test Access Mechanisms that connect to wrapped cores. This paper presents a new test architecture, named the TestRail Architecture, that is a hybrid form of the known Daisychain and Distribution Architectures. An important characteristic of the TestRail Architecture is that it allows for efficient testing of both the cores as well as the core-external circuitry. We present two alternative optimization algorithms for the TestRail Architecture, that minimize the total core-internal test time of the cores in the SOC. These algorithms handle both cores with fixed-length and flexible-length scan chains. Experimental results on three industrial benchmark SOCs show that, compared to previous publications, we obtain comparable or better test times at drastically reduced compute times.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128828202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Spectrum-based BIST in complex SOCs","authors":"Ganapathy Kasturirangan, M. Hsiao","doi":"10.1109/VTS.2002.1011120","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011120","url":null,"abstract":"Presents a spectral built-in-self-test (BIST) for a system-on-a-chip (SOC) environment. Test vectors are generated using the spectral properties of the embedded cores. Because some embedded cores may not have direct connections to the embedded TPG, it would be necessary to test them via other cores. As a result, testing such (cascaded) cores requires considerations on the spectral characteristics of the predecessor and successor cores. Matching spectral characteristics between the outputs of the predecessor core and dominant inputs of the successor core allows the successor core to be more testable. Experimental results for the spectral BIST showed that significantly more faults can be detected using spectral patterns than by conventional weighted random BIST technique.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124444791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Diagnosis of sequence-dependent chips","authors":"C. Li, E. McCluskey","doi":"10.1109/VTS.2002.1011137","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011137","url":null,"abstract":"A technique capable of diagnosing single and multiple stuck-open and stuck-at faults is presented. Eleven sequence-dependent chips (test results depend on the order of test patterns) are diagnosed. Seven of them are diagnosed as having single stuck-open faults. Two of them are diagnosed as having multiple stuck-at and stuck-open faults.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"280 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124495182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reducing time to volume and time to market: Is silicon debug and diagnosis the answer?","authors":"F. Muradali, M. Ricchetti, B. Vermeulen, B. Dervisoglu, B. Gottlieb, B. Koenemann, C. J. Clark","doi":"10.1109/VTS.2002.1011178","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011178","url":null,"abstract":"Advances in semiconductor technology and design automation, together with increased market competition, have driven engineers to achieve higher levels of integration, with shortened development cycles. Consequently, verification and analysis are becoming a major bottleneck for timely design of complex systems. The panelists and the audience will explore silicon debug and its impact on the design cycle.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"136 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120872689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Speeding-up I/sub DDQ/ measurements","authors":"C. Thibeault","doi":"10.1109/VTS.2002.1011157","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011157","url":null,"abstract":"The purpose of this paper is to introduce a new I/sub DDQ/ measurement technique based on active successive approximations, named ASA-I/sub DDQ/. This technique has unique features allowing to speed-up I/sub DDQ/ measurement. Experimental results suggests that a significant speed-up factor can be obtained over the QuiC-Mon technique.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134296023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Test economics for multi-site test with modern cost reduction techniques","authors":"Erik H. Volkerink, A. Khoche, J. Rivoir, K. Hilliges","doi":"10.1109/VTS.2002.1011173","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011173","url":null,"abstract":"Test approaches that can be combined with multisite, like reduced pin-count test, low channel cost ATE, and bandwidth matching, are becoming pervasive. Yet their economic benefits, the tradeoffs, and the long-term scalability of their benefits during technology progress, are not well understood In this paper the benefits and tradeoffs will be analyzed using technical cost modeling. The dependency of the benefits on the application are analyzed by modeling the test cost for 4 different applications. It is shown that the mentioned test approaches can result in a significant and scalable reduction of the Cost of Test.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126243788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Validation and test of network processors and ASICs","authors":"C.-H. Chia, S. Dey, F. Karim, H. Konuk, Keesup Kim","doi":"10.1109/VTS.2002.1011172","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011172","url":null,"abstract":"Rapid growth in the internet and enterprise network traffic, need by both subscribers and operators to provide for differentiated services, and the constant evolution of wireline and wireless networking functions, algorithms and standards, is leading to a high demand for ultra high speed, yet programmable, network processors and ASICs. This session will introduce the design of network processors, and highlight important validation and test challenges associated with network processors and ASICs. The first speaker in this session will review the architecture of a typical OC-192 network processor – a highly complex system-on-chip, consisting of multiple processors, specialized hardware blocks, multiple high-speed embedded memory units, and a highly concurrent and complex on-chip interconnect structure. The talk will analyze the validation and manufacturing test problems of hardware-software GHz network processor chips, which have to use aggressive architecture designs and nano-meter technologies to obtain the required multi-GHz speed, while relying on the presence of multiple processors to provide the necessary flexibility. The second talk will address testing of embedded GHz network processors. In particular, it will describe the challenges faced in testing a specific high-speed low-power network processor chip, which includes two custom-design 64-bit MIPS processors, 0.5MB of L2 cache, and multiple high speed communication blocks, such as gigabit-ethernet, hypertransport, and double-data-rate memory controllers. Some test solutions will be presented, and major test challenges that need to be addressed will be listed. The third talk in this session will address the problem of delay testing in communications chips. In communication devices such as network switches and routers, there usually are multiple unrelated clocks controlling various interfaces and logic. These multiple clock domains presents unique challenges in production testing since it becomes very difficult to predict when the expected output will show up at the pin boundary. The talk will show why delay defects need to be addressed, and how to deal with cycle uncertainty problem during production testing. It will present a novel compaction technique used to deal with the test data volume explosion resulting from including of delay defect screening tests. Proceedings of the 20 th IEEE VLSI Test Symposium (VTS’02) 1093-0167/02 $17.00 © 2002 IEEE","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131810427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}