F. Muradali, M. Ricchetti, B. Vermeulen, B. Dervisoglu, B. Gottlieb, B. Koenemann, C. J. Clark
{"title":"缩短量产时间和上市时间:硅调试和诊断是答案吗?","authors":"F. Muradali, M. Ricchetti, B. Vermeulen, B. Dervisoglu, B. Gottlieb, B. Koenemann, C. J. Clark","doi":"10.1109/VTS.2002.1011178","DOIUrl":null,"url":null,"abstract":"Advances in semiconductor technology and design automation, together with increased market competition, have driven engineers to achieve higher levels of integration, with shortened development cycles. Consequently, verification and analysis are becoming a major bottleneck for timely design of complex systems. The panelists and the audience will explore silicon debug and its impact on the design cycle.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"136 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Reducing time to volume and time to market: Is silicon debug and diagnosis the answer?\",\"authors\":\"F. Muradali, M. Ricchetti, B. Vermeulen, B. Dervisoglu, B. Gottlieb, B. Koenemann, C. J. Clark\",\"doi\":\"10.1109/VTS.2002.1011178\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Advances in semiconductor technology and design automation, together with increased market competition, have driven engineers to achieve higher levels of integration, with shortened development cycles. Consequently, verification and analysis are becoming a major bottleneck for timely design of complex systems. The panelists and the audience will explore silicon debug and its impact on the design cycle.\",\"PeriodicalId\":237007,\"journal\":{\"name\":\"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)\",\"volume\":\"136 \",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-04-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTS.2002.1011178\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTS.2002.1011178","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reducing time to volume and time to market: Is silicon debug and diagnosis the answer?
Advances in semiconductor technology and design automation, together with increased market competition, have driven engineers to achieve higher levels of integration, with shortened development cycles. Consequently, verification and analysis are becoming a major bottleneck for timely design of complex systems. The panelists and the audience will explore silicon debug and its impact on the design cycle.