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Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)最新文献

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Testing static and dynamic faults in random access memories 随机存取存储器中静态和动态故障的测试
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011170
S. Hamdioui, Z. Al-Ars, A. V. Goor
{"title":"Testing static and dynamic faults in random access memories","authors":"S. Hamdioui, Z. Al-Ars, A. V. Goor","doi":"10.1109/VTS.2002.1011170","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011170","url":null,"abstract":"The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverage. The important class of dynamic faults, therefore, cannot be ignored any more. It is shown that conventional memory tests constructed to detect static faulty behavior of a specific defect do not necessarily detect the dynamic faulty behavior. Indeed, dynamic faulty behavior can take place in the absence of static faults. The paper presents new memory tests derived to target the dynamic fault class.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"585 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132843575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 135
Test power reduction through minimization of scan chain transitions 通过最小化扫描链转换来降低测试功率
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011129
O. Sinanoglu, I. Bayraktaroglu, A. Orailoglu
{"title":"Test power reduction through minimization of scan chain transitions","authors":"O. Sinanoglu, I. Bayraktaroglu, A. Orailoglu","doi":"10.1109/VTS.2002.1011129","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011129","url":null,"abstract":"Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result infrequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. No performance degradation ensues as scan chain modifications have no impact on functional execution. A computationally efficient scheme is proposed to identify, the location and type of the logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133225127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 74
Power supply transient signal analysis under real process and test hardware models 电源暂态信号分析下的实际过程和测试硬件模型
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011165
Abhishek Singh, J. Plusquellic, A. Gattiker
{"title":"Power supply transient signal analysis under real process and test hardware models","authors":"Abhishek Singh, J. Plusquellic, A. Gattiker","doi":"10.1109/VTS.2002.1011165","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011165","url":null,"abstract":"A device testing method called Transient Signal Analysis (TSA) is subjected to elements of a real process and testing environment in this paper. Simulation experiments are designed to determine the effects of process skew (obtained from measured parameters of a real process) on the accuracy of TSA in estimating path delays from power supply I/sub DDT/ and V/sub DDT/ waveforms. The circuit model is designed to test TSA under deep submicron process models that incorporate advanced parameters such as transistor V/sub t/ width dependencies. Modeling elements of a testing environment including the probe card are subsequently introduced as a means of evaluating the effects of tester measurement noise in an actual implementation.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127878463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Measuring stray capacitance on tester hardware 在测试硬件上测量杂散电容
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011164
Achintya Halder, A. Chatterjee, P. Variyam, J. Ridley
{"title":"Measuring stray capacitance on tester hardware","authors":"Achintya Halder, A. Chatterjee, P. Variyam, J. Ridley","doi":"10.1109/VTS.2002.1011164","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011164","url":null,"abstract":"Parasitic capacitance in test hardware can affect the performance of a test and lead to poor fault coverage and/or yield loss. In an ATE setup, characterizing the stray capacitance using external instruments is difficult for practical reasons. In this paper, we present a single probe technique that uses available tester resources to measure stray capacitance of test hardware with high accuracy and precision. The proposed method uses a time measurement sub-system and a current source of the ATE for measuring stray capacitance from their charging and discharging characteristics. This capacitance measurement technique is also used to detect and diagnose faults in different tester hardware components. Measurement results and case studies on the application of this technique are presented.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128024893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Test as a key enabler for faster yield ramp-up 测试是快速提高产量的关键推动者
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011135
J. Segal, R. Segers, R. Aitken, S. Eichenberge, A. Gattike, M. Millegen, R. Seger, S. Venkataraman
{"title":"Test as a key enabler for faster yield ramp-up","authors":"J. Segal, R. Segers, R. Aitken, S. Eichenberge, A. Gattike, M. Millegen, R. Seger, S. Venkataraman","doi":"10.1109/VTS.2002.1011135","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011135","url":null,"abstract":"The successful introduction of a new IC manufacturing process requires a rapid yield ramp. In-line inspection, parameter evaluation using special tests structures and memory arrays are typically used to debug and diagnose a new process or product. However, not all the failure mechanisms can be anticipated and detected using such test structures and memory blocks. Logic structures have a different and irregular topology, which may lead to different defect sensitivities. Indeed, some of the (spot) defects may not occur in the test structures or memories and may then only be detected at the product’s final wafer test. Retest, precise electrical fault diagnosis methods and advanced (physical) failure analysis procedures are then needed to localize and characterize these types of failures.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117265996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Approximating infinite dynamic behavior for DRAM cell defects 近似无限动态行为的DRAM单元缺陷
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011171
Z. Al-Ars, A. V. Goor
{"title":"Approximating infinite dynamic behavior for DRAM cell defects","authors":"Z. Al-Ars, A. V. Goor","doi":"10.1109/VTS.2002.1011171","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011171","url":null,"abstract":"Analyzing the dynamic faulty behavior in DRAMs is a severely time consuming task, because of the exponential growth of the analysis time needed with each memory operation added to the sensitizing operation sequence of the fault. In this paper, a new fault analysis approach for DRAM cell defects is presented where the total infinite space of dynamic faulty behavior can be approximated within a limited amount of analysis time. The paper also presents the analysis results for some cell defects using the new approach, in combination with detection conditions that guarantee the detection of any detectable dynamic faults in the defective cell.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121493857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
A method of test generation for path delay faults in balanced sequential circuits 平衡顺序电路中路径延迟故障的测试生成方法
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011160
S. Ohtake, H. Fujiwara, S. Miwa
{"title":"A method of test generation for path delay faults in balanced sequential circuits","authors":"S. Ohtake, H. Fujiwara, S. Miwa","doi":"10.1109/VTS.2002.1011160","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011160","url":null,"abstract":"This paper shows that path delay fault test generation problem for sequential circuits with balanced structure can be reduced to segment delay fault test generation problem for their combinationally transformed circuits. We also propose a test generation method and a partially enhanced scan design method for path delay fault.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132412804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
On test data volume reduction for multiple scan chain designs 多扫描链设计的测试数据量缩减研究
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011119
S. Reddy, K. Miyase, S. Kajihara, I. Pomeranz
{"title":"On test data volume reduction for multiple scan chain designs","authors":"S. Reddy, K. Miyase, S. Kajihara, I. Pomeranz","doi":"10.1109/VTS.2002.1011119","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011119","url":null,"abstract":"We consider issues related to the reduction of scan test data in designs with multiple scan chains. We propose a metric that can be used to evaluate the effectiveness of procedures for reducing the scan data volume. The metric compares the achieved compression to the compression which is intrinsic to the use of multiple scan chains. We also propose a procedure for modifying a given test set so as to achieve reductions in test data volume assuming a combinational decompressor circuit.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131523062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 116
Theorems for efficient identification of indistinguishable fault pairs in synchronous sequential circuits 同步顺序电路中不可区分故障对的有效识别定理
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011136
Enamul Amyeen, I. Pomeranz, W. Fuchs
{"title":"Theorems for efficient identification of indistinguishable fault pairs in synchronous sequential circuits","authors":"Enamul Amyeen, I. Pomeranz, W. Fuchs","doi":"10.1109/VTS.2002.1011136","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011136","url":null,"abstract":"We introduce theorems that enable efficient identification of indistinguishable fault pairs in synchronous sequential circuits using an iterative logic array of limited length. These theorems can be used for identifying fault pairs that can be dropped from. consideration before diagnostic ATPG starts, thus improving the efficiency of diagnostic ATPG. Experimental results are presented to demonstrate the effectiveness of the proposed theorems, which allow us to identify almost all the indistinguishable fault pairs in finite-state machine benchmarks.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131283448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On using rectangle packing for SOC wrapper/TAM co-optimization 基于矩形填料的SOC包装/TAM协同优化研究
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI: 10.1109/VTS.2002.1011146
V. Iyengar, K. Chakrabarty, E. Marinissen
{"title":"On using rectangle packing for SOC wrapper/TAM co-optimization","authors":"V. Iyengar, K. Chakrabarty, E. Marinissen","doi":"10.1109/VTS.2002.1011146","DOIUrl":"https://doi.org/10.1109/VTS.2002.1011146","url":null,"abstract":"The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is therefore necessary for minimizing SOC testing time. We recently proposed an exact technique for co-optimization based on a combination of integer linear programming (ILP) and exhaustive enumeration. However, this approach is computationally expensive for large SOCs, and it is limited to fixed-width test buses. We present a new approach for wrapper/TAM co-optimization based on generalized rectangle packing, also referred to as two-dimensional packing. This approach allows us to decrease testing time by reducing the mismatch between a core's test data needs and the width of the TAM to which it is assigned. We apply our co-optimization technique to an academic benchmark SOC and three industrial SOCs. Compared to the ILP-based technique, we obtain lower or comparable testing times for two out of the three industrial SOCs. Moreover, we obtain more than two orders of magnitude decrease in the CPU time needed for wrapper/TAM co-design.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"547 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114353402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 176
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