平衡顺序电路中路径延迟故障的测试生成方法

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI:10.1109/VTS.2002.1011160

S. Ohtake, H. Fujiwara, S. Miwa

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引用次数: 9

摘要

本文将平衡结构顺序电路的路径延迟故障测试生成问题简化为其组合变换电路的分段延迟故障测试生成问题。提出了一种路径延迟故障的测试生成方法和部分增强扫描设计方法。

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A method of test generation for path delay faults in balanced sequential circuits

This paper shows that path delay fault test generation problem for sequential circuits with balanced structure can be reduced to segment delay fault test generation problem for their combinationally transformed circuits. We also propose a test generation method and a partially enhanced scan design method for path delay fault.

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Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)

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