Test as a key enabler for faster yield ramp-up

Abstract

The successful introduction of a new IC manufacturing process requires a rapid yield ramp. In-line inspection, parameter evaluation using special tests structures and memory arrays are typically used to debug and diagnose a new process or product. However, not all the failure mechanisms can be anticipated and detected using such test structures and memory blocks. Logic structures have a different and irregular topology, which may lead to different defect sensitivities. Indeed, some of the (spot) defects may not occur in the test structures or memories and may then only be detected at the product’s final wafer test. Retest, precise electrical fault diagnosis methods and advanced (physical) failure analysis procedures are then needed to localize and characterize these types of failures.