Logic BIST and scan test techniques for multiple identical blocks

Abstract

In multi-million gate devices, the number of required test patterns may be beyond the limits of current external automatic test equipment (ATE) capabilities. Besides, excessive number of production test vectors results in prohibitive test time that increases the test cost and decreases the production capacity. This paper introduces a new technique to test multiple identical blocks in parallel. The proposed technique can be used either in conjunction with ATE or as a stand-alone BIST technique to test multiple identical blocks on the same chip. The test time and the number of test patterns for testing multiple blocks is only a little bit higher than what is required for testing one block.