长互连信号完整性故障的测试模式生成

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI:10.1109/VTS.2002.1011162

A. Attarha, M. Nourani

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引用次数: 36

摘要

本文提出了一种针对长互连信号完整性故障的测试模式生成算法。这是通过考虑互连的输入和寄生RLC元件的影响来实现的。为了提高测试生成过程的性能，采用了模型降阶方法。该策略显著提高了仿真时间，但精度稍有损失。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Test pattern generation for signal integrity faults on long interconnects

In this paper we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and parasitic RLC elements of the interconnect. To enhance the performance of test generation process, model order reduction methodology is employed. This strategy significantly improves the simulation time with slight loss of accuracy.

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Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)

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