第二十届IEEE VLSI测试研讨会论文集(VTS 2002)

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 1900-01-01 DOI:10.1109/VTS.2002.1011102

{"title":"第二十届IEEE VLSI测试研讨会论文集(VTS 2002)","authors":"","doi":"10.1109/VTS.2002.1011102","DOIUrl":null,"url":null,"abstract":"The following topics are dealt with: microprocessor test; very low voltage testing; DFT testers; test set compression techniques; analog BIST; slow speed testing; test automation; scan-based testing; burn-in reduction; test power; fault diagnosis; analog circuit testing; high level test techniques; SoC test; supply current testing; IEEE P1500; test pattern generation; tester hardware modelling; FPGA test; fault modeling; memory testing; test-cost reduction; and oscillation based test.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)\",\"authors\":\"\",\"doi\":\"10.1109/VTS.2002.1011102\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The following topics are dealt with: microprocessor test; very low voltage testing; DFT testers; test set compression techniques; analog BIST; slow speed testing; test automation; scan-based testing; burn-in reduction; test power; fault diagnosis; analog circuit testing; high level test techniques; SoC test; supply current testing; IEEE P1500; test pattern generation; tester hardware modelling; FPGA test; fault modeling; memory testing; test-cost reduction; and oscillation based test.\",\"PeriodicalId\":237007,\"journal\":{\"name\":\"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)\",\"volume\":\"76 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTS.2002.1011102\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTS.2002.1011102","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

处理以下主题:微处理器测试;极低电压测试;DFT测试人员;测试集压缩技术;模拟阿拉伯学者;慢速测试;测试自动化;scan-based测试;减少老化;测试能力;故障诊断;模拟电路测试;高级测试技术;SoC测试;电源电流测试;IEEE P1500;测试模式生成;测试仪硬件建模;FPGA测试;断层建模;内存测试;减少测试成本;以及基于振荡的测试。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)

The following topics are dealt with: microprocessor test; very low voltage testing; DFT testers; test set compression techniques; analog BIST; slow speed testing; test automation; scan-based testing; burn-in reduction; test power; fault diagnosis; analog circuit testing; high level test techniques; SoC test; supply current testing; IEEE P1500; test pattern generation; tester hardware modelling; FPGA test; fault modeling; memory testing; test-cost reduction; and oscillation based test.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)

自引率

0.00%

发文量