Statistical post-processing at wafersort-an alternative to burn-in and a manufacturable solution to test limit setting for sub-micron technologies

In sub-micron CMOS processes, it has become increasingly difficult to identify and separate outliers from the intrinsic distribution at test. This is due to the increasing inadequacy of reliability screens such as burn-in and IDDQ testing. Statistical Post-Processing (SPP) methods have been developed to run off-tester using the raw data generated from Automatic Test Equipment (ATE) and wafersort maps. Post-Processing modules include advanced IDDQ tests such as Delta IDDQ and the Nearest Neighbor Residual (NNR), as well as other non-IDDQ based reliability-focused modules. This work presents the application and results of SPP at LSI Logic on 0.18 /spl mu/m CMOS products. Challenges of production implementation have been overcome, which include "user definable" adaptive threshold limits, handling multiple data sources, and data flow management. Burn-in data and customer Defects per Million units (DPM) data show a 30-60% decrease in failure rate with SPP implementation with very acceptable yield loss.