一种用于RTL数据路径电路的使用压缩测试表的测试生成方法和使用压缩测试计划表的测试生成方法

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002) Pub Date : 2002-04-28 DOI:10.1109/VTS.2002.1011161

Toshinori Hosokawa, H. Date, M. Muraoka

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引用次数: 7

摘要

针对具有DFT的RTL数据路径电路，提出了一种采用压缩测试表的测试生成方法和一种采用压缩测试计划表的测试生成方法。此外，还提出了一种用于生成压缩测试计划表的启发式算法。与传统的分层测试生成方法相比，该方法可以缩短某些RTL数据路径电路的测试长度。

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A test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits

This paper proposes a test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits with DFT where hierarchical test generations are applicable. Moreover, a heuristic algorithm for a compacted test plan table generation is proposed. The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.

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Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)

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