R. David, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel
{"title":"浅谈高效测试序列的应用","authors":"R. David, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel","doi":"10.1109/VTS.2002.1011126","DOIUrl":null,"url":null,"abstract":"High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution.","PeriodicalId":237007,"journal":{"name":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":"{\"title\":\"On using efficient test sequences for BIST\",\"authors\":\"R. David, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel\",\"doi\":\"10.1109/VTS.2002.1011126\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution.\",\"PeriodicalId\":237007,\"journal\":{\"name\":\"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)\",\"volume\":\"36 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-04-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTS.2002.1011126\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTS.2002.1011126","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution.