2018 IEEE 19th Latin-American Test Symposium (LATS)最新文献

Influence of temperature on dynamic fault behavior due to resistive defects in FinFET-based SRAMs 温度对基于finfet的sram电阻性缺陷动态故障行为的影响

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8349697

G. Medeiros, E. Brum, L. Poehls, T. Copetti, T. Balen

引用次数: 8

RTOS for mixed criticality applications deployed on NoC-based COTS MPSoC 用于混合关键应用的RTOS部署在基于noc的COTS MPSoC上

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8347239

Stefano Esposito, Serhiy Avramenko, M. Violante

引用次数: 3

Probability aware fault-injection approach for SER estimation 基于概率感知的SER估计故障注入方法

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8349692

Fábio B. Armelin, L. Naviner, R. d'Amore

{"title":"Probability aware fault-injection approach for SER estimation","authors":"Fábio B. Armelin, L. Naviner, R. d'Amore","doi":"10.1109/LATW.2018.8349692","DOIUrl":"https://doi.org/10.1109/LATW.2018.8349692","url":null,"abstract":"The Soft-Error Rate (SER) estimation is used to predict how electronic systems will respond to the transient electrical pulses induced by the ionizing radiation. SER estimation by radiation test is an accurate method, but it is expensive and requires the real device. Traditional simulation methods incorporate logical, temporal and electrical masking effects while injecting faults at the output of the device's functional elements. Nevertheless, they do not consider the probability of the ionizing radiation to produce a transient fault at the output of each class of functional element. On the other hand, studies in the stochastic computing domain deal with a probabilistic fault-injection approach. Since many concomitant faults among the elements may occur, the fault probability of each element is treated independently. This leads to the use of one Pseudo-Random Number Generator (PRNG) and a probability comparator for each functional element. However, the analysis of a single fault is usually enough for SER estimation. In this context, this work presents a different approach for probability-aware fault-injection, in which a weighted distribution of faults is defined considering the relative fault probability of each functional element. This approach enables the use of just one PRNG and a decoder for the entire device, instead of a pair ‘PRNG-comparator’ per element, leading to a significant reduction in logic blocks consumption. For the example analyzed in this study, the use of relative fault probability decreases the number of logic blocks from 875 (adopting independent fault probability) to 495.","PeriodicalId":236190,"journal":{"name":"2018 IEEE 19th Latin-American Test Symposium (LATS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129429260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Post-silicon validation based on synthetic test patterns for early detection of timing anomalies 基于早期检测时序异常的综合测试模式的后硅验证

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8347237

Eduardo Garcia-Espinosa, O. Longoria-Gandara, Enrique Gonzalez-Garcia, Arturo Veloz-Guerrero

引用次数: 0

Flexible architecture of memory BISTs 灵活的内存bist架构

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8349666

R. Silveira, Qadeer Qureshi, Rodrigo Zeli

引用次数: 4

Processor core profiling for SEU effect analysis 用于SEU效果分析的处理器核心分析

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8347235

Rodrigo Travessini, P. Villa, F. Vargas, E. Bezerra

引用次数: 16

Reliability evaluation on interfacing with AXI and AXI-S on Xilinx Zynq-7000 AP-SoC Xilinx Zynq-7000 AP-SoC上与axis和axis - s接口的可靠性评估

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8347233

F. Benevenuti, F. Kastensmidt

{"title":"Reliability evaluation on interfacing with AXI and AXI-S on Xilinx Zynq-7000 AP-SoC","authors":"F. Benevenuti, F. Kastensmidt","doi":"10.1109/LATW.2018.8347233","DOIUrl":"https://doi.org/10.1109/LATW.2018.8347233","url":null,"abstract":"This work is set in the context of fault tolerance and reliability of critical cyber-physical systems (CPS) based on state-of-art commercial off-the-shelf (COTS) SRAM-based FPGA devices and, in special, the all programmable system-on-chips (AP-SoC) that are a class of devices combining a general purpose processing system (PS) with custom programmable logic (PL). In SRAM-based FPGAs the Single Event Upsets (SEU) are unavoidable and may alter the contents of storage elements such as flip-flop and, of interest to this work, the configuration memory (CRAM). We analyze the case of Xilinx Zynq-7000, which is based on multi-core ARM processor that, ultimately, provides as one of its major communication interface the ARM Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI). In this context, we analyze reliability of communication interfaces between the embedded processor and the programmable logic and the different hardware modules on each side. For this, we deal with both (1) the development of experimental procedures and tools for fault injection on SRAM-based FPGAs and (2) the development of bottom-up reliability models that would allow estimating system level reliability by aggregating individual reliability from the different hardware modules and communication interfaces obtained from those experimental procedures and tools. In this scenario, fault injection contributes with fine grain reliability evaluation of each component module.","PeriodicalId":236190,"journal":{"name":"2018 IEEE 19th Latin-American Test Symposium (LATS)","volume":"240 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132742196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies 工艺变化对电阻性短缺陷可检测性的影响:28nm Bulk和FDSOI技术的比较分析

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8349696

Amit Karel, F. Azaïs, M. Comte, J. Gallière, M. Renovell

引用次数: 2

IJTAG compatible analogue embedded instruments for MPSoC life-time prediction 用于MPSoC寿命预测的IJTAG兼容模拟嵌入式仪器

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8349691

J. Pathrose, Ghazanfar Ali, H. Kerkhoff

引用次数: 5

A hardware-based approach for SEU monitoring in SRAMs with weak resistive defects 一种基于硬件的弱电阻缺陷ram中SEU监测方法

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8349667

G. Pinto, G. Medeiros, F. Vargas, L. Poehls

{"title":"A hardware-based approach for SEU monitoring in SRAMs with weak resistive defects","authors":"G. Pinto, G. Medeiros, F. Vargas, L. Poehls","doi":"10.1109/LATW.2018.8349667","DOIUrl":"https://doi.org/10.1109/LATW.2018.8349667","url":null,"abstract":"CMOS technology scaling has made the increase of transistor density in Systems-on-Chip (SoC) possible. In addition, the necessity of storing more and more information has resulted in the fact that Static Random Access Memories (SRAMs) have become great part of the SoC's silicon area. This miniaturization brings up several benefits, among them an increase of system performance. However, some undesirable behaviors, that did not exist or that were negligible, now became reality. Manufacturing process variation has introduced new types of defects, such as: (1) Resistive-Open defects and (2) Resistive-Bridge defects, which depending on their size can cause static or dynamic faults. Indeed, the circuit's sensibility to environmental noise is another challenge related to technology scaling. In more detail, the interference can damage the circuit behavior and cause Single Event Upsets (SEUs), affecting the circuit's reliability. Given these circumstances, this work proposes a hardware-based methodology able to detect resistive defects as well as to monitor defective cells in field aiming to detect SEUs. The fundamental idea is to use part of the hardware introduced to perform the manufacturing test to also detect bit-flips during the circuit's lifetime. Note that only SRAM cells with weak resistive defects are monitored, since the cells with strong defects that propagate static faults are isolated after manufacturing test. The proposed work has been validated and evaluated through SPICE simulations adopting an SRAM array modeled with a commercial 65nm CMOS technology library.","PeriodicalId":236190,"journal":{"name":"2018 IEEE 19th Latin-American Test Symposium (LATS)","volume":"176 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127023390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0