Influence of temperature on dynamic fault behavior due to resistive defects in FinFET-based SRAMs

FinFET technology has emerged as the most promising alternative to continue the scaling-down of technological nodes due to its superior electric properties. In parallel, the need to store more information on chip led to Static Random Access Memories (SRAMs) occupying the greatest part of silicon area of Systems-on-Chips (SoCs). During manufacturing, SRAMs can be affected by resistive defects that may lead to dynamic faults, considered one of the most important causes of test escape in deep-submicron technologies. In this context, this paper proposes to analyze the impact of temperature on the dynamic faulty behavior during manufacturing tests of SRAM cells affected by weak resistive defects. In more detail, critical resistances and the number of operations necessary to sensitize faults are investigated. Additionally, the concept of Dynamic Behavior Window is presented and characterized. The proposed analysis has been performed using SPICE simulations adopting a 20nm FinFET compact model.