Rodrigo Travessini, P. Villa, F. Vargas, E. Bezerra
{"title":"用于SEU效果分析的处理器核心分析","authors":"Rodrigo Travessini, P. Villa, F. Vargas, E. Bezerra","doi":"10.1109/LATW.2018.8347235","DOIUrl":null,"url":null,"abstract":"This paper presents the analysis of a fault injection campaign in the CPU registers of the LEON3 softcore processor. The faults are injected through the use of simulation scripts that force a bit flip while the processor is running a set of three different workloads. The study is restricted to single bit upsets (SBU) and investigates the effects of the injected faults and how they propagate to the CPU core boundaries. The obtained results show that the majority of the failures are due to faults injected in only a small number of the processor registers. Furthermore, in this study, it is proposed a partial triple modular redundancy approach to protect only the CPU's most sensitive registers, achieving a 99.25% SBU tolerance with only a marginal increase in area.","PeriodicalId":236190,"journal":{"name":"2018 IEEE 19th Latin-American Test Symposium (LATS)","volume":"os-45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Processor core profiling for SEU effect analysis\",\"authors\":\"Rodrigo Travessini, P. Villa, F. Vargas, E. Bezerra\",\"doi\":\"10.1109/LATW.2018.8347235\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the analysis of a fault injection campaign in the CPU registers of the LEON3 softcore processor. The faults are injected through the use of simulation scripts that force a bit flip while the processor is running a set of three different workloads. The study is restricted to single bit upsets (SBU) and investigates the effects of the injected faults and how they propagate to the CPU core boundaries. The obtained results show that the majority of the failures are due to faults injected in only a small number of the processor registers. Furthermore, in this study, it is proposed a partial triple modular redundancy approach to protect only the CPU's most sensitive registers, achieving a 99.25% SBU tolerance with only a marginal increase in area.\",\"PeriodicalId\":236190,\"journal\":{\"name\":\"2018 IEEE 19th Latin-American Test Symposium (LATS)\",\"volume\":\"os-45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-03-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 19th Latin-American Test Symposium (LATS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LATW.2018.8347235\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 19th Latin-American Test Symposium (LATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LATW.2018.8347235","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents the analysis of a fault injection campaign in the CPU registers of the LEON3 softcore processor. The faults are injected through the use of simulation scripts that force a bit flip while the processor is running a set of three different workloads. The study is restricted to single bit upsets (SBU) and investigates the effects of the injected faults and how they propagate to the CPU core boundaries. The obtained results show that the majority of the failures are due to faults injected in only a small number of the processor registers. Furthermore, in this study, it is proposed a partial triple modular redundancy approach to protect only the CPU's most sensitive registers, achieving a 99.25% SBU tolerance with only a marginal increase in area.