2018 IEEE 19th Latin-American Test Symposium (LATS)最新文献_第5页

Validation of a dynamic checkpoint mechanism for Apache Hadoop with failure scenarios 验证Apache Hadoop的动态检查点机制与失败场景

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-01 DOI: 10.1109/LATW.2018.8347240

Paulo Vinicius Cardoso, P. Barcelos

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引用次数: 9

TDevCGen: A synthesis toolset of HW/SW communication protocol monitors from high-level specifications TDevCGen:来自高级规范的硬件/软件通信协议监视器的综合工具集

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-01 DOI: 10.1109/LATW.2018.8349686

R. Macieira, E. Barros

{"title":"TDevCGen: A synthesis toolset of HW/SW communication protocol monitors from high-level specifications","authors":"R. Macieira, E. Barros","doi":"10.1109/LATW.2018.8349686","DOIUrl":"https://doi.org/10.1109/LATW.2018.8349686","url":null,"abstract":"The use of an electronic embedded system for general or multi-purpose applications has increased substantially and while they require more flexibility for processing different types of applications and communication protocols. The need for this high flexibility also requires the use of general purpose processors as a solution for configuring and controlling a considerable amount of peripherals, what consequently implies in an increasing need for hardware-dependent software (HdS). HdS is a highly critical component and error prone due to the nature of the environment in which it is inserted, and it's hard coding. So it is essential to support the development and runtime phases of HdS by methodologies that are able to capture devices' accesses violations, through the monitoring of the communication protocol specification. So, this paper presents the toolset TDevCGen. This toolset synthesizes properties monitors, for checking hardware/software communication protocol, described through a high-level DSL called TDevC language. Before synthesizing the monitor model (SystemC or SystemVerilog) for runtime validation, the TDevCGen performs a sequence of validation in the specification input, looking for type mismatch, properties inconsistencies and the presence of nondeterministic in the specified protocol. Experiments using a DM9000A Ethernet device and an Altera UART show the efficiency and practicality of proposed approach (TDevCGen). The approach TDevCGen supports the specification of the protocol and communication properties, reducing the time of verification phase significantly, and performs a fast and reliable monitor's synthesis from a high-level specification, eliminating the use of general purpose languages, error-prone coding, and, thus, increasing the reliability of communication checking.","PeriodicalId":236190,"journal":{"name":"2018 IEEE 19th Latin-American Test Symposium (LATS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130837531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Time domain electrical characterization in zinc oxide nanoparticle thin-film transistors 氧化锌纳米颗粒薄膜晶体管的时域电特性

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-01 DOI: 10.1109/LATW.2018.8349695

Thales E. Becker, F. Vidor, G. Wirth, T. Meyers, Julia Reker, U. Hilleringmann

引用次数: 0

A novel method of impact and failure mechanism analysis of RF-based fault injection: A frequency response analyzer, FRA 基于射频的故障注入冲击和失效机理分析新方法:频率响应分析仪，FRA

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-01 DOI: 10.1109/LATW.2018.8349671

L. Kretly, R. Maltione, M. G. Villalva

引用次数: 0