Post-silicon validation based on synthetic test patterns for early detection of timing anomalies

Abstract

Timing anomalies in a system on a chip are one of the most common causes of functional misbehaviors. They are usually hard to find and poses a potential quality risk to the design and implementation of the system. Such anomalies might appear when high-volume validation is performed in the design, which usually takes place at advanced stages of the validation process and close to the product release qualification. In this paper, we propose a methodology to uncover potential timing problems using synthetic test patterns at the beginning of the post-silicon validation process, thus accelerating the timing bugs finding and improving the quality of the samples to be delivered to the customers.