2018 IEEE 19th Latin-American Test Symposium (LATS)最新文献_第2页

Towards evolvable hardware and genetic algorithm operators to fail safe systems achievement 面向可进化硬件和遗传算法算子的故障安全系统实现

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8349669

G. P. Silva, R. O. Duarte

{"title":"Towards evolvable hardware and genetic algorithm operators to fail safe systems achievement","authors":"G. P. Silva, R. O. Duarte","doi":"10.1109/LATW.2018.8349669","DOIUrl":"https://doi.org/10.1109/LATW.2018.8349669","url":null,"abstract":"As systems grow in complexity and extension, the analysis and comprehension of their dynamics becomes proportionally harder, reducing their reliability [1]. Currently, the most common and effective way to deal with faults is through redundancy, although it presents no self-adaptability and is subject to the availability of resources. In this context, it is proposed the investigation and implementation of bio-inspired hardware solutions. It is possible to find systems optimal configurations through the concept of evolution. Therefore, the purpose of this research is to reproduce a novel architecture [2] and analyze the Evolvable Hardware behavior in a FPGA with the capability to self-heal through the search and selection of new optimal hardware configurations assisted by a Genetic Algorithm in order to recover from a hardware service failure caused by component faults [3]. Thereby, it was implemented as a proof of concept a BCD decoder design, which presented a 100% output accuracy and was able to self-adapt, repairing failures caused by simulated faults in up to 35.9% of the cells. The recovery time is affected by the hardware architecture and the evolution operators. Finally, this research concludes that evolvable hardware is a promising alternative for autonomous design and fail-safe digital systems, although it still has potential for improvement and has limited scalability.","PeriodicalId":236190,"journal":{"name":"2018 IEEE 19th Latin-American Test Symposium (LATS)","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121031581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Single event effect: Simulations and analysis on 3N163 PMOS transistor 单事件效应:3N163 PMOS晶体管的仿真与分析

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8349693

Juliano Oliveira, M. Guazzelli, Marco Antonio Assis, R. Giacomini

引用次数: 0

Fault-tolerant architecture with full recovery under presence of SEU 容错架构，在SEU存在下实现完全恢复

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8349670

Augusto Einsfeldt, R. Giacomini

引用次数: 0

Ionizing radiation modeling in DRAM transistors DRAM晶体管中的电离辐射建模

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8349678

M. Fieback, M. Taouil, S. Hamdioui, M. Rovatti

引用次数: 1

Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFs 利用电源斜坡率校准SRAM puf中的单元强度

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8349685

Wendong Wang, A. Singh, Ujjwal Guin, A. Chatterjee

{"title":"Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFs","authors":"Wendong Wang, A. Singh, Ujjwal Guin, A. Chatterjee","doi":"10.1109/LATW.2018.8349685","DOIUrl":"https://doi.org/10.1109/LATW.2018.8349685","url":null,"abstract":"SRAM arrays are particularly attractive for use as physically unclonable functions (PUFs) because each manufactured copy of an SRAM array displays a different memory pattern when initially powered-on. This is due to random differences in device parameters in individual memory cells from manufacturing process variations. However, instability in the SRAM PUF response over the expected range of operating voltages and temperature, as well as environmental noise and aging degradation over time, is a challenge. Recent proposals aim at identifying a subset of all the cells in an SRAM, the most robust or strong cells, and using only these to construct a PUF. However, the manner in which the SRAM is powered up has been largely ignored in earlier work. We show that the SRAM power-up state is strongly dependent on the power supply ramp rate and direction; very different power-up states are obtained under different power-on scenarios. Furthermore, analyzing the power-up states under different ramp rates and directions can provide considerable insight into which transistor pairs in each individual cell are mismatched, and even the extent of the mismatch. Since such threshold voltage mismatch is key to cell power-on bias, we finally show how such experiments can be exploited to reliably identify the most robust strong cells in SRAMs for use in PUFs. These cells can be expected to generating reliable keys for cryptographic operations across a wide range of operating conditions, noise and device degradation.","PeriodicalId":236190,"journal":{"name":"2018 IEEE 19th Latin-American Test Symposium (LATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130182532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Real-time validation of mixed-criticality applications 混合临界应用的实时验证

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8349683

Stefano Esposito, J. Sini, M. Violante

引用次数: 2

A review of approximate computing techniques towards fault mitigation in HW/SW systems 硬件/软件系统故障缓解的近似计算技术综述

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8347241

Alexander Aponte-Moreno, A. Moncada, Felipe Restrepo-Calle, C. Pedraza

引用次数: 19

A flexible stand-alone FPGA-based ATE for ASIC manufacturing tests 用于ASIC制造测试的灵活的独立基于fpga的ATE

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8347236

D. Carvalho, B. Sanches, M. D. Carvalho, W. Noije

引用次数: 4

Defeating hardware Trojan in microprocessor cores through software obfuscation 通过软件混淆击败微处理器内核中的硬件木马

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8349680

A. Marcelli, E. Sánchez, Giovanni Squillero, Muhammad Usman Jamal, Afnan Imtiaz, Simone Machetti, Filippo Mangani, Paolo Monti, D. Pola, Alessandro Salvato, Michele Simili

{"title":"Defeating hardware Trojan in microprocessor cores through software obfuscation","authors":"A. Marcelli, E. Sánchez, Giovanni Squillero, Muhammad Usman Jamal, Afnan Imtiaz, Simone Machetti, Filippo Mangani, Paolo Monti, D. Pola, Alessandro Salvato, Michele Simili","doi":"10.1109/LATW.2018.8349680","DOIUrl":"https://doi.org/10.1109/LATW.2018.8349680","url":null,"abstract":"In recent years a new kind of threat, known as Hardware Trojan, is affecting the Integrated Circuit industry. Un-trusted parties in the supply chain may take advantage of the segmentation in the production to inject malicious hardware components that became active under specific circumstances. As it is impractical to identify such malicious hardware with in-lab testing, most countermeasures are based on hardware alterations, with the drawback of increasing production costs, area, and energy consumption of the final product. In this paper, on the contrary, we propose a software-based, cost-effective solution that minimizes the chance of activation of a multi-stage trigger Hardware Trojan. The approach relies on a pure-software obfuscation mechanism, which exploits an evolutionary algorithm to modify an executable program without affecting its functionalities. Such obfuscation can be used to protect critical infrastructures and operations with a reduced and predictable loss of performances. The proposed technique has been evaluated against a well-known real-world hardware attack, getting positive and promising results concerning its effectiveness.","PeriodicalId":236190,"journal":{"name":"2018 IEEE 19th Latin-American Test Symposium (LATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130882040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Direct optimization of a PCI express link equalization in industrial post-silicon validation 工业后硅验证中PCI快速链路均衡的直接优化

2018 IEEE 19th Latin-American Test Symposium (LATS) Pub Date : 2018-03-12 DOI: 10.1109/LATW.2018.8347238

F. Rangel-Patiño, J. Rayas-Sánchez, Edgar-Andrei Vega-Ochoa, N. Hakim

{"title":"Direct optimization of a PCI express link equalization in industrial post-silicon validation","authors":"F. Rangel-Patiño, J. Rayas-Sánchez, Edgar-Andrei Vega-Ochoa, N. Hakim","doi":"10.1109/LATW.2018.8347238","DOIUrl":"https://doi.org/10.1109/LATW.2018.8347238","url":null,"abstract":"Post-silicon validation is a crucial industrial testing process in modern computer platforms. Post-silicon validation of high-speed input/output (HSIO) links can be critical for making a product release qualification. Peripheral component interconnect express (PCIe) is a high-performance interconnect architecture widely adopted in the computer industry, and one of the most complex HSIO interfaces. PCIe data rates increase on every new generation. To mitigate channel effects due to the increase in transmission speeds, the PCIe specification defines requirements to perform equalization (EQ) at the transmitter (Tx) and at the receiver (Rx). During the EQ process, one combination of Tx/Rx EQ coefficients must be selected to meet the performance requirements of the system. Testing all possible coefficient combinations is prohibitive. Current industrial practice consists of finding a subset of combinations at post-silicon validation using maps of EQ coefficients, which are obtained by measuring the eye height, eye width, and the eye asymmetries of the received signal. Given the large number of electrical parameters and the multiplicity of signal eyes that are produced by on-die probes for observation, finding this subset of coefficients is often a challenge. In order to overcome this problem, a direct optimization method based on a suitable objective function formulation to efficiently tune the Tx and Rx EQ coefficients to successfully comply with the PCIe specification is presented in this report. The proposed optimization approach is based on a low-cost computational procedure combining pattern search and Nelder-Mead methods to efficiently solve an objective function with many local minima, and evaluated by lab measurements on a realistic industrial post-silicon validation platform.","PeriodicalId":236190,"journal":{"name":"2018 IEEE 19th Latin-American Test Symposium (LATS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125928791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5