2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)最新文献_第2页

A Reliable PUF in a Dual Function SRAM 双功能SRAM中的可靠PUF

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464143

Mohd Syafiq Mispan, Shengyu Duan, Basel Halak, Mark Zwolinski

{"title":"A Reliable PUF in a Dual Function SRAM","authors":"Mohd Syafiq Mispan, Shengyu Duan, Basel Halak, Mark Zwolinski","doi":"10.1109/PATMOS.2018.8464143","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464143","url":null,"abstract":"An SRAM Physical Unclonable Function (SRAM-PUF) is a potential solution for lightweight secure key generation, and is particularly suitable for resource-constrained security devices. An SRAM-PUF is able to generate random and unique cryptographic keys based on start-up values (SUVs) by exploiting intrinsic manufacturing process variations. For cost efficiency the available on-chip SRAM in a system can be reused as a PUF. As CMOS technology scales down, ageing-induced Negative Bias Temperature Instability (NBTI) becomes more pronounced, resulting in asymmetric degradation of memory bit cells after prolonged storage of the same bit values. This causes unreliable SUVs for an SRAM-PUF. In this paper, we investigate the bit probabilities in an instruction cache and the effect on long-term reliability. We show that the signal probability in a 32-bit ARM instruction cache has a predictable pattern. Hence, we propose a bit selection technique to mitigate the NBTI effect when an instruction cache is used as a PUF. We show that this technique can reduce the predicted bit error in an SRAM-PUF from 14.18% to 5.58% over 5 years. Consequently, as the bit error reduces, the area overhead of the error-correction is about $6 times$ smaller compared to that without a bit selection technique.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114701482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

A Battery-Less BLE IoT Motion Detector Supplied by 2.45-GHz Wireless Power Transfer 2.45 ghz无线电力传输提供的无电池BLE物联网运动检测器

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464144

R. Dekimpe, Pengcheng Xu, Maxime Schramme, D. Flandre, D. Bol

{"title":"A Battery-Less BLE IoT Motion Detector Supplied by 2.45-GHz Wireless Power Transfer","authors":"R. Dekimpe, Pengcheng Xu, Maxime Schramme, D. Flandre, D. Bol","doi":"10.1109/PATMOS.2018.8464144","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464144","url":null,"abstract":"Wireless power transfer (WPT) is a possible way to achieve cheap, rapid and large-scale deployment of battery-less IoT smart sensors. However, the key challenge in designing WPT-supplied smart sensors is to ensure that the harvested power is higher than the consumed power in presence of strong WPT path loss. This paper presents the design and optimization of a smart sensor supplied by 2.45-GHz RF power and performing infrared-based motion detection and Bluetooth Low Energy (BLE) communication. The full system (RF energy harvester, power management, sensor transducer and interface, control, data processing and wireless transmission) is implemented using low-power off-the-shelf components. In the sensing sub-system, low average power is achieved using efficient duty-cycling of the analog front-end. In the harvesting sub-system, architecture choice and design of the matching network and rectifier circuit allow to optimize the total power harvesting efficiency (PHE). The implemented smart sensor can operate reliably with an incident RF power as low as −10.9 dBm. The sensing sub-system exhibits an average power of 4.3 μW and a maximum number of transmitted event packets of 60 packets per hour.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120945292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Hardware Implementation of a Low-Power K-Best MIMO Detector Based on a Hybrid Merge Network 基于混合合并网络的低功耗K-Best MIMO检测器的硬件实现

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464169

Ibrahim A. Bello, Basel Halak, M. El-Hajjar, Mark Zwolinski

引用次数: 2

Mobile Terminals System-Level Memory Exploratio for Power and Performance Optimization 用于功率和性能优化的移动终端系统级存储器探索

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464166

Amal Ben Ameur, M. Auguin, F. Verdier, V. Frascolla

{"title":"Mobile Terminals System-Level Memory Exploratio for Power and Performance Optimization","authors":"Amal Ben Ameur, M. Auguin, F. Verdier, V. Frascolla","doi":"10.1109/PATMOS.2018.8464166","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464166","url":null,"abstract":"Mobile devices, at each new release of the standards and following users' continuous requests of new services, have to support more and more features, which are also becoming more and more demanding from the computational point of view. As a consequence, being able to fulfil new requirements and at the same time to provide power efficient chips is nowadays the most important challenge for mobile devices system designers. To tackle this challenge, novel system level performance and power modeling approaches have been proposed allowing hardware/software (HW/SW) architectures to be explored right at the very first steps of a System-on-Chip (SoC) design flow. However, existing solutions have limited support for the power optimization of the memory system (including SDRAM) that may occupy more than 70% of a chip area and consume more than 30% of the total energy. In this paper, we propose a SystemC-TLM-based simulation framework at Electronic System Level (ESL), which is able to support the joint exploration of a SoC architecture and its memory configuration. This new framework helps in optimizing the SoC energy consumption while matching the required performance in terms of power and performance, as well as of memory bandwidth and latency.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123020284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

TSV Assignment of Thermal and Wirelength Optimization for 3D-IC Routing 3D-IC路由的TSV分配和带宽优化

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464161

Yi Zhao, Cong Hao, T. Yoshimura

引用次数: 4

Effect of Temperature Variation in Experimental DPA and DEMA Attacks 温度变化对实验性DPA和DEMA攻击的影响

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8463993

E. Tena-Sánchez, A. Acosta

{"title":"Effect of Temperature Variation in Experimental DPA and DEMA Attacks","authors":"E. Tena-Sánchez, A. Acosta","doi":"10.1109/PATMOS.2018.8463993","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8463993","url":null,"abstract":"Side-Channels attacks are usually performed to measure the vulnerability of cryptocircuits against malicious attacks. The conditions in which the attacks are carried out have influence in their effectivity. In this sense, temperature variations should be considered to assess the complete vulnerability of a system, but they have not been deeply considered in the literature. For this purpose, experimental DPA and DEMA attacks are carried out over one of the widest used and studied block cipher, namely AES algorithm, implemented in a Spartan-6 FPGA. The effectivity of DPA and DEMA attacks under different temperatures: 10, 25, 50 and 70°C have been studied experimentally. The attacks have been made over the 128 bits of two randomly chosen keys. The security achieved for each attack is measured using the Measurements to Disclose (MTD) the key, which determines the minimum number of patterns needed to retrieve the secret key. From the results we can obtain interesting conclusions: DPA attack is more effective than the DEMA attack over the AES implementation on FPGA. On the other hand, we conclude that the key has influence on the MTD value, but the variability between keys is of the same magnitude as the variability between temperatures, meaning that temperature variation is not a decisive factor in the effectiveness of an attack.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114280384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Quantitative Evaluation of Certain SET Mitigation Techniques for Multiply-Accumulate Circuits and State Machines 若干多重累积电路和状态机的SET缓解技术的定量评价

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464165

Vassilis Paliouras, K. Karagianni, Yann Oster

引用次数: 0

Testing Framework for in-Hardware Verification of the Hardware Modules Generated Using HLS HLS生成硬件模块的硬件内验证测试框架

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464157

Julián Caba, Fernando Rincón Calle, J. Dondo, Jesús Barba, Manuel J. Abaldea, J. C. López

{"title":"Testing Framework for in-Hardware Verification of the Hardware Modules Generated Using HLS","authors":"Julián Caba, Fernando Rincón Calle, J. Dondo, Jesús Barba, Manuel J. Abaldea, J. C. López","doi":"10.1109/PATMOS.2018.8464157","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8464157","url":null,"abstract":"High-Level Synthesis (HLS) allows Field Programmable Gate Array (FPGA) developers to easily implement complex applications in silicon, addressing the ever-growing size and complexity of modern embedded reconfigurable systems. Unfortunately, in spite of these advancements, new non-negligible verification problems arise. For instance, the co-simulation strategy may not provide trustworthy results due to the variable accuracy of simulation, or hardware synthesis issues (e.g. those related to signal routing) which are not detectable in the simulation. Hence, developers need new verification mechanisms to reduce the gap between the technology and the verification needs. In this paper, we propose a testing framework and a hardware verification platform based on FPGA technology in order to improve the verification accuracy and enable effortless and fully automatic in-hardware system validation. For instance, one of the mechanisms is the inclusion of physical configuration macros (e.g., clock rate configuration macro) and test assertions based on physical parameters in the verification environment (e.g., timing assertions). Experiment results demonstrate our approach in the context of a case study remaining the same testing technology independently of the module abstraction level.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133536981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard Applications 智能卡应用的对称功率分析攻击弹性绝热逻辑

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8463996

H. S. Raghav, V. A. Bartlett, I. Kale

{"title":"Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard Applications","authors":"H. S. Raghav, V. A. Bartlett, I. Kale","doi":"10.1109/PATMOS.2018.8463996","DOIUrl":"https://doi.org/10.1109/PATMOS.2018.8463996","url":null,"abstract":"On the whole existing secure adiabatic logic designs exhibit variations in current peaks and have asymmetric structures. However, asymmetric structure and variations in current peaks make the circuit vulnerable to Power Analysis Attacks (PAA). In this paper, we shall present a novel PAA resilient adiabatic logic which has a symmetric structure and exhibits the least variations in current peaks for basic gates as well as in 8-bit Montgomery multiplier. The proposed logic has been compared with two recently proposed secure adiabatic logic designs for operating frequencies ranging from 1MHz to 100MHz and power-supply scaling ranging from 0.6V to 1.8V. Simulation results of the gates show that our proposed logic exhibits the lowest Normalized Energy Deviation (NED) and Normalized Standard Deviation (NSD) under the said frequency variations. All the 2-input gates that deploy the proposed logic dissipate nearly the same average energy within 0.2% of each other at all the frequencies simulated and thus, along with the data-independence, gate-function-independence is achieved. The paper will also report on the energy dissipated by the proposed logic which approaches that of the existing logic designs as the output load capacitance is increased above 100fF. The simulation results of the 8-bit adiabatic Montgomery multiplier show that the proposed logic exhibits the least value of NED and NSD under the said frequency variations and power-supply scaling. Finally, the paper will report on the current waveform graphs for variations in current peaks under power-clock scaling.","PeriodicalId":234100,"journal":{"name":"2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123537205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure 利用混合存储器结构最大化片上缓存的能源效率

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) Pub Date : 2018-07-01 DOI: 10.1109/PATMOS.2018.8464141

Hongjie Xu, Jun Shiomi, T. Ishihara, H. Onodera

引用次数: 2