Hardware Implementation of a Low-Power K-Best MIMO Detector Based on a Hybrid Merge Network

Multiple input multiple output (MIMO) technology is anticipated to play a key role in future wireless communications systems. However, one of the main challenges of MIMO technology is the high complexity of the signal detection, which results in a high power consumption at the MIMO receiver. In this paper, we present the hardware implementation of a $K$-best detector based on a single-stage architecture, targeted at low-rate and low-power applications. To achieve a low complexity, we optimise the sorting stage of the detector by systematically eliminating redundant comparators. Furthermore, the sorter incorporates different merge algorithms at selected stages in order to reduce the total comparator count. For a 64-QAM $4 \times 4$ MIMO system, the detector achieves a power consumption of 34 mW using the STMicroelectronics 65 nm CMOS library, which compares favourably with similar works from the literature.